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公开(公告)号：US11134256B1
公开(公告)日：2021-09-28
申请号：US16745163
申请日：2020-01-16
Applicant: Xilinx, Inc.
Inventor： Avinash Ramachandran , Pavel Novotny
IPC: H04N7/12 , H04N19/436 , H04N19/91 , H04N19/176 , H04N19/152 , H04N19/115 , H04N19/164 , H04N19/127
Abstract: Methods and systems for parallelized encoding of video are disclosed. According to one embodiment, a video encoder comprises a plurality of encoding engines. Each encoding engine is configured to receive a respective designated region of a video frame and produce respective quantized coefficients, the respective region having one or more unencoded frame blocks. Each encoding engine has a local symcoder for performing entropy-based encoding of the respective quantized coefficients. The video encoder has a rate control module, in communication with each encoding engine, for receiving from the respective local symcoder of each encoding engine a respective region-level bit count. The video encoder has a central buffer, in communication with each encoding engine, for receiving from each encoding engine the respective quantized coefficients. The video encoder has a final symcoder, in communication with the central buffer and the rate control module, wherein the final symcoder performs further entropy-based encoding of the respective quantized coefficients received in the central buffer, and transmits to the rate control module a frame-level bit count.
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公开(公告)号：US11134140B2
公开(公告)日：2021-09-28
申请号：US15481350
申请日：2017-04-06
Applicant: Xilinx, Inc.
Inventor： Steve L. Pope , David J. Riddoch
Abstract: A data processing system is provided. A host processing device supports a host transport engine operable to establish a first transport stream over a network with a remote peer. Device hardware comprises a device transport engine. The device transport engine is configured to monitor the first transport stream to determine a state of the first transport stream and in response to an indication from the host processing device perform transport processing of the first transport stream.
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公开(公告)号：US11133963B1
公开(公告)日：2021-09-28
申请号：US17011595
申请日：2020-09-03
Applicant: Xilinx, Inc.
Inventor： Kevin Zheng , Ronan Casey
Abstract: Apparatus and associated methods relate to targeted digital correction of a predetermined component of inter-symbol interference (ISI) associated with two or more ranks of cascaded track-and-hold (T/H) front-end circuits of a Time-Interleaved analog-to-digital converter (TI-ADC). In an illustrative example, for two T/H circuit ranks of size N and M, the predetermined component to be compensated may be located at (N×M)th unit interval (UI). A feed forward equalizer (FFE) and/or a decision feedback equalizer (DFE) in a digital signal processing system (DSP) may be then configured to have extra taps and corresponding expanded equalization ranges to mitigate the ISI. Thus, a deterministic ISI component at the N×Mth UI may be digitally corrected by providing equalization with N×M taps at low cost to facilitate scaling to higher bit rates.
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公开(公告)号：US11127718B2
公开(公告)日：2021-09-21
申请号：US16741319
申请日：2020-01-13
Applicant: XILINX, INC.
Inventor： Anil Kumar Kandala , Vijay Kumar Koganti , Santosh Yachareni
IPC: H01L21/00 , H01L25/065 , H01L23/48 , H01L23/528 , H01L23/00 , H01L25/00
Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within dielectric layers disposed on a side of the semiconductor substrate of the respective chip. The first and second continuous portions are aligned in a direction normal to the side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal line. An output node of the selection circuit is connected to the other of the first or second metal line.
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公开(公告)号：US11127442B2
公开(公告)日：2021-09-21
申请号：US16706437
申请日：2019-12-06
Applicant: Xilinx, Inc.
Inventor： Xiaoqian Zhang , Ephrem C. Wu , David Berman
Abstract: An integrated circuit (IC) includes a plurality of dies. The IC includes a plurality of memory channel interfaces configured to communicate with a memory, wherein the plurality of memory channel interfaces are disposed within a first die of the plurality of dies. The IC may include a compute array distributed across the plurality of dies and a plurality of remote buffers distributed across the plurality of dies. The plurality of remote buffers are coupled to the plurality of memory channels and to the compute array. The IC further includes a controller configured to determine that each of the plurality of remote buffers has data stored therein and, in response, broadcast a read enable signal to each of the plurality of remote buffers initiating data transfers from the plurality of remote buffers to the compute array across the plurality of dies.
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Patent Agency Ranking
公开(公告)号：US11119956B2
公开(公告)日：2021-09-14
申请号：US15633566
申请日：2017-06-26
Applicant: Xilinx, Inc.
Inventor： Steve Leslie Pope , David James Riddoch
Abstract: A network interface device capable of communication with a data processing system supporting an operating system and at least one application, the network interface device supporting communication with the operating system by means of: two or more data channels, each data channel being individually addressable by the network interface device and being capable of carrying application-level data between the network interface device and the data processing device; and a control channel individually addressable by the network interface device and capable of carrying control data between the network interface device, the control data defining commands and the network interface being responsive to at least one command sent over the control channel to establish at least one additional data channel.
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公开(公告)号：US20210281499A1
公开(公告)日：2021-09-09
申请号：US17328941
申请日：2021-05-24
Applicant: Xilinx, Inc.
Inventor： Steven L. POPE , David J. RIDDOCH , Derek ROBERTS
Abstract: A network interface device, said network interface device has a data transmission path configured to receive data for transmission. The data for transmission is to be sent over a network by the network interface device. A monitor is configured to monitor the data transmission path to determine if an underrun condition is associated with the data transmission path. If so, an indication is included in the transmitted data packet.
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公开(公告)号：US20210281251A1
公开(公告)日：2021-09-09
申请号：US16812130
申请日：2020-03-06
Applicant: Xilinx, Inc.
Inventor： Roswald Francis , Christophe Erdmann
Abstract: A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.
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公开(公告)号：US11114429B2
公开(公告)日：2021-09-07
申请号：US16392460
申请日：2019-04-23
Applicant: Xilinx, Inc.
Inventor： James Karp
IPC: H01L27/02 , H01L25/065 , H01L23/60 , H01L23/31
Abstract: Disclosed herein are integrated circuit devices and methods for fabricating the same that include at least one non-I/O die having ESD protection circuitry. The ESD protection circuitry disclosed herein may also be utilized in I/O dies. In one example, an integrated circuit device includes a die having a first body. First and second contact pads are exposed to a surface of the first body. The first contact pad is configured to connect to a first supply voltage. The second contact pad is configured to connect to a second supply voltage or ground. A first charge-sensitive circuitry formed in the first body is coupled between the first and second contact pads. A first RC clamp formed in the first body is coupled between the first and second contact pads. The first RC clamp includes at least two BigFETs coupled between the first and second contact pads, and a trigger circuitry coupled in parallel to gate terminals of the at least two BigFETs.
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公开(公告)号：US11114360B1
公开(公告)日：2021-09-07
申请号：US16580620
申请日：2019-09-24
Applicant: XILINX, INC.
Inventor： Jaspreet Singh Gandhi , Myongseob Kim
IPC: H01L25/065 , H01L23/31 , H01L21/3065 , H01L23/498 , H01L21/56
Abstract: Examples described herein provide techniques for multi-die device structures having improved gap uniformity between neighboring dies. In some examples, a first die and a second die are attached to an interposer. A first gap is defined by and between the first die and the second die. At least one of the first die or the second die is etched at the first gap. The etching defines a second gap defined by and between the first die and the second die. The first die, the second die, and the interposer are encapsulated with an encapsulant. The encapsulant is disposed in the second gap.
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