公开(公告)号：US20230067396A1

公开(公告)日：2023-03-02

申请号：US17463152

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera ,  Yen Chun Lee ,  Ferdinando Bedeschi

IPC: G11C11/4074 ,  G11C11/4096 ,  G11C7/10

Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a plurality of read voltages to the memory array based on the read request. The control circuit is further configured to perform a data analysis for a first set of data read based on the application of the plurality of read voltages and to derive a demarcation bias voltage (VDM) based on the data analysis. The control circuit is also configured to apply the VDM to the memory array to read a second set of data.

公开(公告)号：US20230060231A1

公开(公告)日：2023-03-02

申请号：US18049855

申请日：2022-10-26

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Jessica Chen ,  Nevil Gajera

IPC: G11C13/00

Abstract: Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

公开(公告)号：US20230058300A1

公开(公告)日：2023-02-23

申请号：US17980396

申请日：2022-11-03

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera

IPC: G11C11/56 ,  G11C7/10

Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells without having bit values stored in the memory cells to include an identifier of the programming mode. During the test of which of the memory cells in the set is in a lowest voltage region, which is a common operation for reading the memory cells programmed in different mode, the statistics of the memory cells found to be in the lowest voltage region can be compared to the known, different behaviors of the memory cell set programmed in different modes. A match with the behavior of one of the modes can be used to identify the matching mode as the programming mode of the set of memory cells.

公开(公告)号：US20230032006A1

公开(公告)日：2023-02-02

申请号：US17885136

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Lorenzo Fratin ,  Fabio Pellizzer

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memory array. The first vertical n-type transistor may be configured to selectively couple an access line with a source node and the second n-type transistor may be configured to selectively couple the access line with a ground node. To activate the access line coupled with the first and second vertical n-type transistors, the first vertical n-type transistor may be activated, the second vertical n-type transistor may be deactivated, and the source node coupled with the first vertical n-type transistor may have a voltage applied that differs from a ground voltage.

公开(公告)号：US11545625B2

公开(公告)日：2023-01-03

申请号：US17100185

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Kolya Yastrebenetsky ,  Fabio Pellizzer

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.

公开(公告)号：US11545216B2

公开(公告)日：2023-01-03

申请号：US17165555

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Jessica Chen ,  Nevil Gajera

IPC: G11C13/00

Abstract: Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

公开(公告)号：US11489117B2

公开(公告)日：2022-11-01

申请号：US17308444

申请日：2021-05-05

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

IPC: H01L45/00 ,  H01L27/24

Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

公开(公告)号：US20220319615A1

公开(公告)日：2022-10-06

申请号：US17221420

申请日：2021-04-02

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.

公开(公告)号：US20220302212A1

公开(公告)日：2022-09-22

申请号：US17833596

申请日：2022-06-06

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera ,  Lei Wei

IPC: H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  H01L23/532

Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

公开(公告)号：US20220302211A1

公开(公告)日：2022-09-22

申请号：US17431661

申请日：2020-07-22

Applicant: Micron Technology, Inc.

Inventor： Lorenzo Fratin ,  Paolo Fantini ,  Fabio Pellizzer

IPC: H01L27/24 ,  H01L45/00

Abstract: Methods for, apparatuses with, and vertical 3D memory devices are described. A vertical 3D memory device may comprise: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from one another by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a dielectric material positioned between the first plurality and the second plurality of word line plates, the dielectric material extending in a serpentine shape over the substrate; a plurality of pillars formed over and coupled with the plurality of contacts; and a plurality of storage elements each comprising chalcogenide material positioned in a recess between a respective word line plate and a respective pillar, wherein the recess is of an arch-shape, and the chalcogenide material in the recess contacts the respective word line plate.