公开(公告)号：US20220320066A1

公开(公告)日：2022-10-06

申请号：US17806895

申请日：2022-06-14

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L25/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a microelectronic device comprises forming a source material around substantially an entire periphery of a base material, and removing the source material from lateral sides of the base material while maintaining the source material over an upper surface and a lower surface of the base material. Related methods and base structures for microelectronic devices are also described.

公开(公告)号：US11380669B2

公开(公告)日：2022-07-05

申请号：US16905734

申请日：2020-06-18

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L25/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a microelectronic device comprises forming a source material around substantially an entire periphery of a base material, and removing the source material from lateral sides of the base material while maintaining the source material over an upper surface and a lower surface of the base material. Related methods and base structures for microelectronic devices are also described.

公开(公告)号：US20220181344A1

公开(公告)日：2022-06-09

申请号：US17115469

申请日：2020-12-08

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Surendranath C. Eruvuru

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/06 ,  H01L27/092 ,  H01L21/8234

Abstract: An electronic device includes one or more capacitors adjacent to a base material. The one or more capacitors comprise at least one electrode extending horizontally within the base material, and additional electrodes extending vertically within the base material and contacting the at least one electrode. The at least one electrode is located below and isolated from an upper surface of the base material. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US20220157844A1

公开(公告)日：2022-05-19

申请号：US17590266

申请日：2022-02-01

Applicant: Micron Technology, Inc.

Inventor： M. Jared Barclay ,  Merri L. Carlson ,  Saurabh Keshav ,  George Matamis ,  Young Joon Moon ,  Kunal R. Parekh ,  Paolo Tessariol ,  Vinayak Shamanna

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11565

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

公开(公告)号：US11282815B2

公开(公告)日：2022-03-22

申请号：US16742485

申请日：2020-01-14

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

IPC: H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

公开(公告)号：US20220059560A1

公开(公告)日：2022-02-24

申请号：US17000809

申请日：2020-08-24

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/00 ,  H01L23/532 ,  H01L23/522

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure. The microelectronic device structure comprises a semiconductive base structure, and a memory array region vertically overlying the semiconductive base structure and comprising memory cells. The microelectronic device structure is attached to a base structure. A portion of the semiconductive base structure is removed after attaching the microelectronic device structure to a base structure. A control logic region is formed vertically over a remaining portion of the semiconductive base structure. The control logic region comprises control logic devices in electrical communication with the memory cells of the memory array region. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.

公开(公告)号：US20210351201A1

公开(公告)日：2021-11-11

申请号：US17383988

申请日：2021-07-23

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/06 ,  H01L21/768 ,  H01L21/02 ,  H01L21/762

Abstract: Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210143165A1

公开(公告)日：2021-05-13

申请号：US17125639

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Justin B. Dorhout ,  Nancy M. Lomeli

IPC: H01L27/11556 ,  G11C16/08 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L29/788 ,  H01L27/11524

Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.

公开(公告)号：US10998326B2

公开(公告)日：2021-05-04

申请号：US16907858

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/768 ,  H01L27/112 ,  H01L21/67 ,  H01L21/3215 ,  H01L27/11524 ,  H01L27/11551 ,  H01L21/308 ,  H01L21/033 ,  H01L27/11553 ,  H01L27/1157

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200328222A1

公开(公告)日：2020-10-15

申请号：US16382932

申请日：2019-04-12

Applicant: Micron Technology, Inc.

Inventor： M. Jared Barclay ,  Merri L. Carlson ,  Saurabh Keshav ,  George Matamis ,  Young Joon Moon ,  Kunal R. Parekh ,  Paolo Tessariol ,  Vinayak Shamanna

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/311

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.