公开(公告)号：US5508679A

公开(公告)日：1996-04-16

申请号：US303172

申请日：1994-09-08

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G06F5/06 ,  H03K5/22

CPC分类号： G06F5/06

摘要： Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status through the use of programmable, resettable counters which eliminate the need for subtractor circuitry. A comparator is used to compare a value from a read counter with a value from a write counter. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. Offset of the read count from the write count is accomplished by utilizing counters which provide programmable resettability. Use of programmable, resettable counters allows FIFO flag values to be chosen and implemented very easily. For instance, it is possible for a user to change from an almost full FIFO flag to a half full FIFO flag without changing any hardware at all. The counters are simply programmed and reset accordingly.

摘要翻译： 适用于FIFO存储器的差分标志逻辑被修改为通过使用可编程的可复位计数器来快速生成FIFO标志状态，从而消除对减法器电路的需要。 比较器用于将来自读计数器的值与来自写计数器的值进行比较。 通过将写入计数的读取计数与期望的FIFO标志值相等的值来抵消减法器功能。 通过使用提供可编程可重定位性的计数器来实现从写入计数读取计数的偏移。 使用可编程的可复位计数器可以非常容易地选择和实现FIFO标志值。 例如，用户可以从几乎完全的FIFO标志变为半完整的FIFO标志，而不改变任何硬件。 计数器被简单地编程并相应地复位。

公开(公告)号：US5502678A

公开(公告)日：1996-03-26

申请号：US315337

申请日：1994-09-30

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C29/50 ,  G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41

摘要： According to the present invention, a first memory block of the memory chip is placed into the long write test mode, meaning that all wordlines of the first memory block are turned off and the voltages on all the bitlines of the first memory block are controlled such that either all the bitlines true of a memory block are equal to a low logic level, all the bitlines complement of the memory block are equal to the low logic level, or all the bitlines true and bitlines complement of the memory block are both equal to the low logic level. Next, a second memory block of the memory chip is likewise placed into the long write test mode, while the first memory block remains in the long write test mode. After a long pause which causes a long write disturb condition, the memory blocks of the memory chip are one by one taken out of the long write test and read disturbed. Then, the rows of the first memory block are selected, one by one, in minimal cycle time to read disturb the first memory block. Next, the second memory block of the memory chip is likewise placed into the read disturb mode, while the first memory block is deselected and thus not affected.

摘要翻译： 根据本发明，存储芯片的第一存储块被放置在长写测试模式中，这意味着第一存储块的所有字线被截止，并且第一存储块的所有位线上的电压被控制为 存储器块的所有位线都等于低逻辑电平，存储器块的所有位线补码都等于低逻辑电平，或者所有位线都为真，并且存储器块的位线补码都等于 逻辑电平低。 接下来，存储器芯片的第二存储器块同样被放置在长写入测试模式中，而第一存储器块保持在长写入测试模式。 在长时间的暂停之后，导致长的写入干扰状况，存储芯片的存储块从长写入测试中逐个取出并且被读取干扰。 然后，以最小的周期时间逐个选择第一存储器块的行以读取第一存储器块的干扰。 接下来，存储芯片的第二存储块同样被放置在读取干扰模式中，而第一存储块被取消选择并且因此不受影响。

公开(公告)号：US5502655A

公开(公告)日：1996-03-26

申请号：US221986

申请日：1994-04-01

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C7/00 ,  G01R29/027 ,  G06F5/10 ,  G06F5/12 ,  G06F7/02 ,  H03K5/26 ,  G06F19/00

CPC分类号： G06F5/12 ,  G01R29/0273 ,  G06F7/026 ,  G06F2205/126

摘要： A first-in first-out (FIFO) memory includes flag generation circuitry indicating the relative fullness of the memory. A write and a read counter count the number of read and write clock signals used to read to and write from the memory. A subtractor circuit receives the values in the counters as inputs, and generates a difference signal as an output. This difference signal is then compared to a program value, and a flag generated indicating the relative magnitudes of the difference value and the program value. Several different program values can be utilized to generate several different flags for the memory.

摘要翻译： 先进先出（FIFO）存储器包括指示存储器的相对丰满度的标志产生电路。 写入和读取计数器计数用于从存储器读取和写入的读取和写入时钟信号的数量。 减法器电路接收计数器中的值作为输入，并产生差分信号作为输出。 然后将该差信号与程序值进行比较，生成的标志指示差值和程序值的相对大小。 可以使用几个不同的程序值来为存储器生成几个不同的标志。

公开(公告)号：US5493532A

公开(公告)日：1996-02-20

申请号：US251337

申请日：1994-05-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C29/46 ,  G11C7/00

CPC分类号： G11C29/46

摘要： An integrated memory circuit having special stress test mode capability, and that is safely controlled by edge transition detection, is disclosed. The memory includes a test mode enable circuit that generates a test mode enable signal responsive to receiving overvoltage signals or other codes at terminals of the memory; the test mode enable signal is presented to the edge transition detection circuitry, so that the edge transition detection pulse that would otherwise initiate a memory operation is not generated during special test mode. This prevents the disastrous possibility that memory functions would be initiated by false edge transition detection signals (such as may occur during ramping of supply voltages to stress levels) during the special test mode. Special tests, such as stress tests and long write cycle disturb tests, may thus be safely performed.

摘要翻译： 公开了一种具有特殊应力测试模式能力并由边缘转变检测安全控制的集成存储器电路。 存储器包括测试模式使能电路，其响应于在存储器的端子处接收过电压信号或其他代码而产生测试模式使能信号; 测试模式使能信号被呈现给边沿转换检测电路，使得否则将在特殊测试模式期间产生否则将启动存储器操作的边沿转换检测脉冲。 这防止了在特殊测试模式期间存储器功能将由伪边沿跳变检测信号（例如在电源电压到压力水平的斜坡期间发生）而发生的灾难性可能性。 因此，可以安全地执行特殊测试，例如压力测试和长写周期干扰测试。

公开(公告)号：US5473567A

公开(公告)日：1995-12-05

申请号：US298766

申请日：1994-08-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C7/062 ,  G11C7/065

摘要： A memory system that includes a memory array having at least two pairs of data lines, first and second data lines that correspond to columns in the memory array. The memory array also includes two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to the first data lines and a second disabling sense amplifier circuit connected to the second data lines, wherein the disabling sense amplifier circuits produce output signals and may be enabled and disabled. A selection signal is provided for selectively enabling and disabling the disabling sense amplifier circuits, wherein one pair of data lines may be selected. An amplification circuit connected to the disabling sense amplifier circuits provides for amplifying the output signals from the disabling sense amplifier circuits.

摘要翻译： 一种存储器系统，其包括具有至少两对数据线的存储器阵列，对应于存储器阵列中的列的第一和第二数据线。 存储器阵列还包括两个禁用读出放大器电路，连接到第一数据线的第一禁用读出放大器电路和连接到第二数据线的第二禁用读出放大器电路，其中禁用读出放大器电路产生输出信号并且可以被使能 并禁用。 提供选择信号用于选择性地启用和禁用禁用读出放大器电路，其中可以选择一对数据线。 连接到禁用读出放大器电路的放大电路提供放大来自禁用读出放大器电路的输出信号。

公开(公告)号：US5457647A

公开(公告)日：1995-10-10

申请号：US40664

申请日：1993-03-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C7/12 ,  G11C7/18 ,  H01L29/04

CPC分类号： G11C7/18 ,  G11C7/12

摘要： In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitline. Local select signals, when set to the appropriate voltage level, couple a local bitline to the master bitline. In addition to reducing the local bitline capacitance that must be driven by memory cells, the hierarchical configuration may provide layout area savings as well.

摘要翻译： 在诸如SRAM，DRAM，EPROM或EEPROM的高密度存储器中，利用分级位线配置，使得通过将本地位线连接到主位线的接口电路将多个本地位线连接到主位线。 本地选择信号，当设置为适当的电压电平时，将本地位线耦合到主位线。 除了减少必须由存储器单元驱动的本地位线电容之外，层级配置也可以节省布局面积。

公开(公告)号：US5424986A

公开(公告)日：1995-06-13

申请号：US811088

申请日：1991-12-19

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/83 ,  G11C29/78

摘要： An integrated circuit memory having redundant rows, for replacing a row in a primary array having a defective memory cell, is disclosed. For each primary row that is to be replaced, a fuse is opened between the output of the row decoder and the word line for the replaced row. A power-on reset circuit is provided in the memory for determining if the power supply voltage has reached an adequate voltage; if not, a transistor connected to each word line is turned on, biasing the word line to a de-energizing voltage. This ensures that the word lines for replaced rows do not power up in an "on" state.

摘要翻译： 公开了一种具有冗余行的集成电路存储器，用于替换具有缺陷存储单元的初级阵列中的行。 对于要替换的每个主行，在行解码器的输出和替换行的字线之间打开一个保险丝。 在存储器中提供上电复位电路，用于确定电源电压是否已经达到足够的电压; 如果不是，则连接到每个字线的晶体管导通，将字线偏置为断电电压。 这确保替换行的字线在“开”状态下不起动。

公开(公告)号：US5424985A

公开(公告)日：1995-06-13

申请号：US170612

申请日：1993-12-20

申请人： David C. McClure ,  William C. Slemmer

发明人： David C. McClure ,  William C. Slemmer

IPC分类号： G11C11/41 ,  G11C7/06 ,  G11C7/22 ,  G11C11/417 ,  H01L27/10 ,  G11C13/00

CPC分类号： G11C7/22 ,  G11C7/06

摘要： Circuits and methods for generating a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device is disclosed. In a first embodiment, a delay circuit is provided for generating an output clock signal for controlling a circuit internal to an integrated circuit, such as a clocked sense amplifier in a memory device, relative to an earlier timing signal, such as a row select signal. The delay circuit is implemented by components having their design parameters, such as transistor dimensions and transistor orientation, corresponding to elements in an active portion of the circuit, such as memory cell transistors. Process variations that affect the electrical properties and the speed of the transistors in the active portion of the circuit will similarly affect the electrical properties and speed of transistors in the delay circuit, so the delay circuit can track and automatically compensate for process-induced speed variations, eliminating the need for large design time margins. Alternative embodiments are also disclosed which account for the threshold voltage drops across pass transistors in a memory array, and mimic the memory cell read current, when generating a sense amplifier clock signal.

摘要翻译： 公开了用于产生延迟添加到半导体器件中将第一电路的输出计时到第二电路的输入的时钟信号的电路和方法。 在第一实施例中，提供延迟电路，用于产生用于控制集成电路内部的电路的输出时钟信号，诸如存储器件中的定时读出放大器相对于较早的定时信号，例如行选择信号 。 延迟电路由具有它们的设计参数（诸如晶体管尺寸和晶体管取向）的元件实现，对应于诸如存储单元晶体管的电路的有源部分中的元件。 影响电路的有效部分中的晶体管的电性能和速度的工艺变化将类似地影响延迟电路中的晶体管的电性能和速度，因此延迟电路可以跟踪并自动补偿工艺引起的速度变化 ，消除了对设计时间裕度大的需求。 还公开了替代实施例，其考虑了存储器阵列中跨越晶体管的阈值电压降，并且在产生读出放大器时钟信号时模拟存储器单元读取电流。

公开(公告)号：US5402379A

公开(公告)日：1995-03-28

申请号：US114749

申请日：1993-08-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1048

摘要： A method and apparatus for an improved precharge device for an internal bus of an integrated circuit. Multiple precharge devices connect to signal lines throughout an internal bus. The multiple precharge devices are distributed along the internal as opposed to a single precharge device at one end utilized prior thereto. The present invention reduces the time necessary to precharge signal lines due to the decreased effective RC time delay affecting each precharge device.

摘要翻译： 一种用于集成电路的内部总线的改进的预充电装置的方法和装置。 多个预充电装置通过内部总线连接到信号线。 多个预充电装置沿着内部分布，而不是单个预充电装置在其之前使用的一端。 由于影响每个预充电装置的有效RC时间延迟减小，本发明减少了对信号线预充电所需的时间。

公开(公告)号：US5400007A

公开(公告)日：1995-03-21

申请号：US020045

申请日：1993-02-19

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G06F7/02

CPC分类号： G06F7/026

摘要： A magnitude comparator is modified to compare the magnitudes of two large binary values more quickly and with minimum gate delays. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby reducing magnitude comparator delay. These compare output signals are fed into a control element which determines which compare output signal is allowed to pass through as the final compare output signal. This circuitry, along with logic circuitry which indicates whether corresponding bit values within associated groups exactly match, defines a magnitude comparator block. Multiple magnitude blocks are used to facilitate the comparison of larger binary values. Each magnitude comparator block generates a compare output signal which, in turn, is an input to a corresponding gating element. Each gating element possesses a logic input signal, derived in part from its magnitude comparator block's match logic circuitry. The gating element logic input signals ensure that only the compare output signal of the magnitude comparator block having the highest order bits with magnitude difference will be allowed to propagate through as the final compare output signal.

摘要翻译： 修改幅度比较器，以更快速地和最小门延迟比较两个大二进制值的幅度。 位比较器被分成彼此并联的比较输出信号的组，从而减小幅度比较器的延迟。 这些比较输出信号被馈送到控制元件，该控制元件确定哪个比较输出信号被允许通过作为最终的比较输出信号。 该电路连同逻辑电路一起指示相关联组中的对应位值是否完全匹配，定义了幅度比较器块。 使用多个幅度块来促进较大二进制值的比较。 每个幅度比较器块产生比较输出信号，该比较输出信号又是对应的门控元件的输入。 每个门控元件都具有逻辑输入信号，部分来自其幅度比较器块的匹配逻辑电路。 门控元件逻辑输入信号确保只有具有幅度差异的最高阶位的幅度比较器块的比较输出信号将被允许传播通过作为最终比较输出信号。