公开(公告)号：US06281555B1

公开(公告)日：2001-08-28

申请号：US09187861

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01K2976

CPC classification number: H01L21/76237 ,  H01L21/26506 ,  H01L21/2658

Abstract: An integrated circuit is provided having an improved packing density due to an improved isolation structure between a plurality of devices on the substrate. An ultra shallow trench isolation structure is provided, typically having a trench depth just deeper than the doped regions of a transistor or other device placed thereon, but substantially shallower than the depth of a well associated with the transistor. A nitrogen ion implantation step is utilized to fabricate an implanted portion beneath the insulative portion, the implanted portion extending preferably below the depth of the well. Due to a shallower trench isolation structure, the structure may also be narrower, providing for improved packing density in a semiconductor device.

Abstract translation: 提供了一种集成电路，由于衬底上的多个器件之间的改进的隔离结构而具有改进的封装密度。 提供了一种超浅沟槽隔离结构，其通常具有刚好比放置在其上的晶体管或其它器件的掺杂区域更深的沟槽深度，但是基本上比与晶体管相关联的阱的深度浅。 使用氮离子注入步骤来制造在绝缘部分下方的植入部分，所述注入部分优选地延伸到井的深度之下。 由于较浅的沟槽隔离结构，结构也可能更窄，从而提供了半导体器件中改善的封装密度。

公开(公告)号：US06271095B1

公开(公告)日：2001-08-07

申请号：US09255546

申请日：1999-02-22

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L29/665

Abstract: A method of fabricating an integrated circuit with locally confined deep pocket regions utilizes a dummy or sacrificial gate spacer. Dopants are provided through the openings associated with sacrificial spacers to form the pocket regions. The dopants are provided after silicidation. The openings can be filled with spacers. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有局部密封深口袋区域的集成电路的方法利用虚拟或牺牲栅极间隔物。 通过与牺牲间隔物相关联的开口提供掺杂剂以形成袋区域。 在硅化后提供掺杂剂。 开口可以填充间隔件。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06248637B1

公开(公告)日：2001-06-19

申请号：US09405831

申请日：1999-09-24

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28202 ,  H01L21/28123 ,  H01L29/41783 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66492 ,  H01L29/665

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on a substrate. The MOSFETs include elevated source and drain regions. The elevated source and drain regions are adjacent ultra-shallow source and drain regions. Dopants in the ultra-shallow source and drain regions are activated in a low-temperature rapid thermal anneal process.

Abstract translation: 超大规模集成（ULSI）电路在衬底上包括MOSFET。 MOSFET包括升高的源极和漏极区域。 升高的源极和漏极区域是相邻的超浅源极和漏极区域。 在超浅源极和漏极区域中的掺杂剂在低温快速热退火工艺中被激活。

公开(公告)号：US06228721B1

公开(公告)日：2001-05-08

申请号：US09602666

申请日：2000-06-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L218234

CPC classification number: H01L21/823462 ,  Y10S438/981

Abstract: For fabricating a metal oxide structure on a semiconductor substrate, an active device area surrounded by at least one STI (shallow trench isolation) structure is formed in the semiconductor substrate. A layer of metal is deposited on the semiconductor substrate, and the layer of metal contacts the active device area of the semiconductor substrate. A layer of oxygen blocking material is deposited on the layer of metal. An opening is etched through the layer of oxygen blocking material to expose an area of the layer of metal on top of the active device area. A thermal oxidation process is performed to form a metal oxide structure from reaction of oxygen with the area of the layer of metal that is exposed. A thickness of the metal oxide structure is determined by a thickness of the layer of metal, and the layer of oxygen blocking material prevents contact of oxygen with the layer of metal such that the metal oxide structure is formed localized at the area where the layer of metal is exposed. In this manner, the metal oxide structure is formed by localized thermal oxidation of the layer of metal such that a deposition or sputtering process or an etching process is not necessary for formation of the metal oxide structure. In addition, the thickness of the metal oxide structure is determined by controlling the thickness of the layer of metal used for forming the metal oxide structure. Furthermore, these steps may be repeated for another layer of metal having a different thickness for forming a plurality of metal oxide structures having different thicknesses to provide gate dielectrics of MOSFETs (metal oxide semiconductor field effect transistors) having different threshold voltages on the same semiconductor substrate.

Abstract translation: 为了在半导体衬底上制造金属氧化物结构，在半导体衬底中形成由至少一个STI（浅沟槽隔离）结构包围的有源器件区域。 一层金属沉积在半导体衬底上，金属层与半导体衬底的有源器件区接触。 一层氧阻塞材料沉积在金属层上。 通过氧阻挡材料层蚀刻开口以暴露活性器件区域顶部的金属层的区域。 进行热氧化处理以形成金属氧化物结构，从氧与暴露的金属层的面积的反应。 金属氧化物结构的厚度由金属层的厚度确定，并且氧阻挡材料层防止氧与金属层的接触，使得金属氧化物结构形成在区域 金属被暴露。 以这种方式，通过金属层的局部热氧化形成金属氧化物结构，使得形成金属氧化物结构不需要沉积或溅射工艺或蚀刻工艺。 此外，通过控制用于形成金属氧化物结构的金属层的厚度来确定金属氧化物结构的厚度。 此外，可以对具有不同厚度的另一层金属重复这些步骤，以形成具有不同厚度的多个金属氧化物结构，以在同一半导体衬底上提供具有不同阈值电压的MOSFET（金属氧化物半导体场效应晶体管）的栅极电介质 。

公开(公告)号：US06225176B1

公开(公告)日：2001-05-01

申请号：US09255203

申请日：1999-02-22

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6656

Abstract: A method of fabricating an integrated circuit with a step source/drain junction utilizes a triple amorphization technique. The technique creates a shallow amorphous region, an intermediate region and a deep amorphous region. The doped amorphous regions can be laser-annealed to form step-like source/drain junctions and their extensions. The process can be utilized for P-channel or N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs).

Abstract translation: 制造具有阶跃源极/漏极结的集成电路的方法利用三次非晶化技术。 该技术产生浅的非晶区域，中间区域和深非晶区域。 掺杂的非晶区域可以被激光退火以形成阶梯状源极/漏极结及其延伸。 该过程可用于P沟道或N沟道金属氧化物半导体场效应晶体管（MOSFET）。

公开(公告)号：US6165849A

公开(公告)日：2000-12-26

申请号：US205616

申请日：1998-12-04

Applicant: Judy X. An ,  Bin Yu

Inventor： Judy X. An ,  Bin Yu

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L21/823462

Abstract: A semiconductor device is formed having a low voltage transistor in a logic core portion and a high voltage transistor in an input/output portion. The low voltage transistor is formed by ion implanting nitrogen into the surface and forming a gate oxide layer on the nitrogen implanted surface portion of the semiconductor substrate in the logic core region. The implanted nitrogen retards the growth of the gate oxide layer in the nitrogen implanted area, thereby enabling formation of gate oxide layers having different thicknesses.

Abstract translation: 半导体器件形成为具有逻辑芯部分中的低电压晶体管和输入/输出部分中的高压晶体管。 低压晶体管通过将氮离子注入到表面中并在逻辑核心区域中的半导体衬底的氮注入表面部分上形成栅极氧化物层而形成。 植入的氮阻止氮注入区域中的栅极氧化物层的生长，从而能够形成具有不同厚度的栅极氧化物层。

公开(公告)号：US6066533A

公开(公告)日：2000-05-23

申请号：US163290

申请日：1998-09-29

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/8234

CPC classification number: H01L21/82345

Abstract: A method for making a ULSI MOSFET includes depositing a high-k gate insulator on a silicon substrate and then depositing a field oxide layer over the gate insulator. The field oxide layer is masked with photoresist and the photoresist patterned to establish first gate windows, and the oxide below the windows is then etched away to establish first gate voids in the oxide. The first gate voids are filled with a first metallic gate electrode material that is suitable for establishing a gate electrode of, e.g., an N-channel MOSFET. Second gate voids are similarly made in the oxide and filled with a second gate electrode material that is suitable for establishing a gate electrode of, e.g., an P-channel MOSFET or another N-channel MOSFET having a different threshold voltage than the first MOSFET. With this structure, plural threshold design voltages are supported in a single ULSI chip that uses high-k gate insulator technology.

Abstract translation: 制造ULSI MOSFET的方法包括在硅衬底上沉积高k栅极绝缘体，然后在栅极绝缘体上沉积场氧​​化物层。 用光致抗蚀剂掩蔽场氧化物层，并且将光致抗蚀剂图案化以建立第一栅极窗口，然后蚀刻掉窗口下面的氧化物以在氧化物中建立第一栅极空隙。 第一栅极空隙填充有适于建立例如N沟道MOSFET的栅电极的第一金属栅电极材料。 第二栅极空隙类似地在氧化物中制成并且填充有适于建立例如P沟道MOSFET或具有不同于第一MOSFET的阈值电压的另一N沟道MOSFET的栅电极的第二栅电极材料。 利用这种结构，在使用高k栅极绝缘体技术的单个ULSI芯片中支持多个阈值设计电压。

公开(公告)号：US09584265B2

公开(公告)日：2017-02-28

申请号：US14369403

申请日：2012-03-09

Applicant: Weiwei Yang ,  Bo Dai ,  Chunli Liang ,  Bin Yu ,  Shuqiang Xia

Inventor： Weiwei Yang ,  Bo Dai ,  Chunli Liang ,  Bin Yu ,  Shuqiang Xia

IPC: H04W72/02 ,  H04W72/04 ,  H04L1/18 ,  H04L5/00 ,  H04L1/00 ,  H04L5/14

CPC classification number: H04L1/1861 ,  H04L1/0073 ,  H04L5/001 ,  H04L5/0055 ,  H04L5/1469 ,  H04W72/02 ,  H04W72/0413

Abstract: Provided are a method and apparatus for sending Hybrid Automatic Repeat Request Acknowledge (HARQ-ACK) information. The method includes: when a terminal employs a physical uplink control channel (PUCCH) format 3 to transmit HARQ-ACK information and the HARQ-ACK information is transmitted over a uplink physical shared channel (PUSCH), determining the number of downlink subframes for serving cells to feed back the HARQ-ACK information; determining the number of encoded modulated symbols required for sending the HARQ-ACK information according to the determined number of downlink subframes; and mapping the HARQ-ACK information to be sent to the PUSCH of a specified uplink subframe according to the number of encoded modulated symbols and sending the HARQ-ACK information. The technical solutions provided by the disclosure are applied to improve the performance of the HARQ-ACK information, and thus improve the data performance.

Abstract translation: 提供了一种用于发送混合自动重传请求确认（HARQ-ACK）信息的方法和装置。 该方法包括：当终端采用物理上行链路控制信道（PUCCH）格式3来发送HARQ-ACK信息，并且通过上行链路物理共享信道（PUSCH）发送HARQ-ACK信息时，确定用于服务的下行链路子帧的数量 小区来反馈HARQ-ACK信息; 根据确定的下行链路子帧的数量确定发送HARQ-ACK信息所需的编码调制符号的数量; 以及根据编码的调制符号的数量映射要发送到指定上行链路子帧的PUSCH的HARQ-ACK信息，并发送HARQ-ACK信息。 应用本公开提供的技术方案来改进HARQ-ACK信息的性能，从而提高数据性能。

公开(公告)号：US09564995B2

公开(公告)日：2017-02-07

申请号：US14385685

申请日：2012-06-25

Applicant: Xiaobo Zhang ,  Bin Yu ,  Wenfeng Zhang

Inventor： Xiaobo Zhang ,  Bin Yu ,  Wenfeng Zhang

IPC: H04J3/00 ,  H04L1/08 ,  H04B7/26 ,  H04L5/14 ,  H04W72/04 ,  H04W76/04 ,  H04L1/18 ,  H04L5/00 ,  H04W88/02

CPC classification number: H04L1/08 ,  H04B7/2656 ,  H04L1/1812 ,  H04L1/1854 ,  H04L1/1861 ,  H04L1/1893 ,  H04L5/003 ,  H04L5/0053 ,  H04L5/14 ,  H04W72/042 ,  H04W76/27 ,  H04W88/02

Abstract: A retransmission method for a time division duplexing self-adaptive frame structure, and a network side device relate to a technology of dynamically allocating uplink and downlink sub-frames in an LTE-advance (3GPP Release11) TDD communication system. The method comprises: during transmission of a TDD self-adaptive frame, for an uplink sub-frame, if a frame structure, of which an RTT period of PHICH and PUSCH of the uplink sub-frame is 10 ms, corresponding to the uplink sub frame is found in 7 types of defined frame structures, then sending PHICH data on a corresponding downlink sub-frame in the found frame structure, and sending retransmission data on the corresponding uplink sub-frame in the found frame structure. The solution ensures HARQ compatibility of an uplink data channel of R10UE. In addition, A/N feedback of the PDSCH is configured according to the uplink A/N resolution, thereby improving retransmission performance.

Abstract translation: 一种用于时分双工自适应帧结构的重传方法，以及网络侧设备涉及在LTE-advance（3GPP Release 11）TDD通信系统中动态分配上行链路和下行链路子帧的技术。 该方法包括：在传输TDD自适应帧期间，对于上行链路子帧，如果其中PHICH和上行链路子帧的PUSCH的RTT周期为10ms的帧结构对应于上行链路子帧 在7种定义的帧结构中找到帧，然后在所找到的帧结构中的相应下行子帧上发送PHICH数据，并在找到的帧结构中的相应上行链路子帧上发送重发数据。 该解决方案确保了R10UE的上行链路数据信道的HARQ兼容性。 另外，根据上行A / N分辨率配置PDSCH的A / N反馈，从而提高重发性能。

公开(公告)号：US09374809B2

公开(公告)日：2016-06-21

申请号：US14374578

申请日：2011-12-21

Applicant: Bo Dai ,  Bin Yu ,  Peng Hao ,  Chunli Liang ,  Shuqiang Xia

Inventor： Bo Dai ,  Bin Yu ,  Peng Hao ,  Chunli Liang ,  Shuqiang Xia

IPC: H04W72/04 ,  H04L5/00 ,  H04L1/18 ,  H04J3/00 ,  H04W72/02 ,  H04L5/14

CPC classification number: H04W72/0413 ,  H04J3/00 ,  H04L1/1861 ,  H04L5/001 ,  H04L5/0053 ,  H04L5/0098 ,  H04L5/1469 ,  H04W72/02

Abstract: The present invention provides a method and user equipment for transmitting a physical uplink control channel. The method includes: in a carrier aggregation scenario, based on a predetermined rule, the transmission of the Physical Uplink Control Channel (PUCCH) is switched between a secondary component carrier and a primary component carrier, or the transmission of the PUCCH is only in the primary component carrier, which is selected by the user equipment (UE); and the UE transmitting the PUCCH in the selected component carrier. The present invention reduces the feedback time delay of uplink control information, and improves the utilization of uplink resources.

Abstract translation: 本发明提供一种用于发送物理上行链路控制信道的方法和用户设备。 该方法包括：在载波聚合场景中，基于预定规则，物理上行链路控制信道（PUCCH）的传输在次分量载波和主分量载波之间切换，或者PUCCH的传输仅在 由用户设备（UE）选择的主分量载波; 并且UE在所选择的分量载波中发送PUCCH。 本发明减少了上行链路控制信息的反馈时间延迟，提高了上行资源的利用率。