公开(公告)号：US06245618B1

公开(公告)日：2001-06-12

申请号：US09243487

申请日：1999-02-03

Applicant: Judy X. An ,  Bin Yu

Inventor： Judy X. An ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66537 ,  H01L21/26506 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/66545

Abstract: A semiconductor device with improved short channel characteristics is formed with a buried amorphous region comprising a retrograde impurity region having the impurity concentration peak of the semiconductor substrate. The buried amorphous region, formed below the channel region, suppresses diffusion of displaced atoms and holes from the source/drain regions and reduces the resistance against latch-up phenomenon, thereby improving short channel characteristics.

Abstract translation: 具有改善的短沟道特性的半导体器件形成有包括具有半导体衬底的杂质浓度峰的逆向杂质区的埋入非晶区。 形成在沟道区下方的埋入非晶区域抑制了位移原子和空穴从源极/漏极区的扩散，并降低了对闭锁现象的抵抗力，从而改善了短沟道特性。

公开(公告)号：US6051470A

公开(公告)日：2000-04-18

申请号：US231651

申请日：1999-01-15

Applicant: Judy X. An ,  Bin Yu

Inventor： Judy X. An ,  Bin Yu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66484 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/66545

Abstract: A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions and central conductive portion. The edge conductive portions provide high potential barriers against the active regions, thereby reducing threshold voltage roll off and leakage current.

Abstract translation: 具有减少的热载流子注入和穿通的半导体器件由双栅极电极形成，该双栅电极包括边缘导电部分，中心导电部分和形成在边缘导电部分和中心导电部分之间的电介质侧壁间隔物。 边缘导电部分提供抵抗有源区域的高电势势垒，从而降低阈值电压滚降和漏电流。

公开(公告)号：US6165849A

公开(公告)日：2000-12-26

申请号：US205616

申请日：1998-12-04

Applicant: Judy X. An ,  Bin Yu

Inventor： Judy X. An ,  Bin Yu

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L21/823462

Abstract: A semiconductor device is formed having a low voltage transistor in a logic core portion and a high voltage transistor in an input/output portion. The low voltage transistor is formed by ion implanting nitrogen into the surface and forming a gate oxide layer on the nitrogen implanted surface portion of the semiconductor substrate in the logic core region. The implanted nitrogen retards the growth of the gate oxide layer in the nitrogen implanted area, thereby enabling formation of gate oxide layers having different thicknesses.

Abstract translation: 半导体器件形成为具有逻辑芯部分中的低电压晶体管和输入/输出部分中的高压晶体管。 低压晶体管通过将氮离子注入到表面中并在逻辑核心区域中的半导体衬底的氮注入表面部分上形成栅极氧化物层而形成。 植入的氮阻止氮注入区域中的栅极氧化物层的生长，从而能够形成具有不同厚度的栅极氧化物层。

公开(公告)号：US06696725B1

公开(公告)日：2004-02-24

申请号：US09527227

申请日：2000-03-16

Applicant: Judy X. An ,  Bin Yu

Inventor： Judy X. An ,  Bin Yu

IPC: H01L31119

CPC classification number: H01L29/66484 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7831

Abstract: A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions and central conductive portion. The edge conductive portions provide high potential barriers against the active regions, thereby reducing threshold voltage roll off and leakage current.

Abstract translation: 具有减少的热载流子注入和穿通的半导体器件由双栅极电极形成，该双栅电极包括边缘导电部分，中心导电部分和形成在边缘导电部分和中心导电部分之间的电介质侧壁间隔物。 边缘导电部分提供抵抗有源区域的高电势势垒，从而降低阈值电压滚降和漏电流。

公开(公告)号：US6153538A

公开(公告)日：2000-11-28

申请号：US303627

申请日：1999-05-03

Applicant: Judy X. An

Inventor： Judy X. An

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/51 ,  H01L21/469

CPC classification number: H01L21/28202 ,  H01L21/0214 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/26526 ,  H01L21/2822 ,  H01L21/31662 ,  H01L29/518 ,  H01L29/6659

Abstract: A semiconductor device comprising a miniaturized transistor with high-speed performance is formed with an ultra thin gate oxide layer. The ultra thin gate oxide layer is formed retarding its growth on a nitrogen-rich silicon substrate. Embodiments include ion implanting impurity to displace nitrogen atoms from a nitride layer on the substrate and to force the displaced nitrogen atoms into the surface portion of the semiconductor substrate. The nitrogen atoms retard the growth of the gate oxide layer, thereby enabling formation of an ultra thin gate oxide.

Abstract translation: 包括具有高速性能的小型化晶体管的半导体器件由超薄栅极氧化物层形成。 形成超薄栅极氧化物层延迟其在富氮硅衬底上的生长。 实施方案包括离子注入杂质以从衬底上的氮化物层置换氮原子并迫使置换的氮原子进入半导体衬底的表面部分。 氮原子延缓了栅极氧化物层的生长，从而能够形成超薄栅极氧化物。

公开(公告)号：US07844927B2

公开(公告)日：2010-11-30

申请号：US11655534

申请日：2007-01-19

Applicant: Zhi-Yuan Wu ,  Ali Icel ,  Judy X. An ,  Ciby T. Thuruthiyil

Inventor： Zhi-Yuan Wu ,  Ali Icel ,  Judy X. An ,  Ciby T. Thuruthiyil

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation. The method further includes verifying convergence of the quality assured semiconductor device model.

Abstract translation: 根据一个示例性实施例，当升级半导体器件工艺的至少一个关键参数时，用于产生质量有保证的半导体器件模型的方法包括：验证半导体器件的质量保证模型与测量数据或预测目标的一致性。 该方法还包括当多个关键参数之一变化时，验证半导体器件的质量保证模型的准确性和一致性。 该方法还包括验证保证质量的半导体器件模型与旧的半导体器件模型的一致性。 该方法还包括在多个半导体器件依赖性中的每一个的范围内验证保证质量的半导体器件模型。 该方法还包括验证用于数字电路操作的质量保证的半导体器件模型。 该方法还包括验证用于模拟电路操作的质量保证的半导体器件模型。 该方法还包括验证质量保证的半导体器件模型的收敛。

公开(公告)号：US6136674A

公开(公告)日：2000-10-24

申请号：US245727

申请日：1999-02-08

Applicant: Judy X. An ,  Che-Hoo Ng

Inventor： Judy X. An ,  Che-Hoo Ng

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L21/3205

CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/42368 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device is formed having a gate electrode and a gate oxide comprising a central portion and edge portions having a thickness greater than that of the edge portions. Nitrogen is ion implanted into the surface of the semiconductor substrate to retard the growth of the central portion of the gate oxide, thereby enabling formation of gate oxide having a thin central portion and thicker edge portions.

Abstract translation: 形成具有栅电极和栅氧化物的半导体器件，栅极氧化物包括中心部分和具有大于边缘部分的厚度的边缘部分。 将氮离子注入到半导体衬底的表面中以阻止栅极氧化物的中心部分的生长，从而能够形成具有薄的中心部分和较厚的边缘部分的栅极氧化物。

公开(公告)号：US20080177523A1

公开(公告)日：2008-07-24

申请号：US11655534

申请日：2007-01-19

Applicant: Zhi-Yuan Wu ,  Ali Icel ,  Judy X. An ,  Ciby T. Thuruthiyil

Inventor： Zhi-Yuan Wu ,  Ali Icel ,  Judy X. An ,  Ciby T. Thuruthiyil

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation. The method further includes verifying convergence of the quality assured semiconductor device model.

Abstract translation: 根据一个示例性实施例，当升级半导体器件工艺的至少一个关键参数时，用于产生质量有保证的半导体器件模型的方法包括：验证半导体器件的质量保证模型与测量数据或预测目标的一致性。 该方法还包括当多个关键参数之一变化时，验证半导体器件的质量保证模型的准确性和一致性。 该方法还包括验证保证质量的半导体器件模型与旧的半导体器件模型的一致性。 该方法还包括在多个半导体器件依赖性中的每一个的范围内验证保证质量的半导体器件模型。 该方法还包括验证用于数字电路操作的质量保证的半导体器件模型。 该方法还包括验证用于模拟电路操作的质量保证的半导体器件模型。 该方法还包括验证质量保证的半导体器件模型的收敛。

公开(公告)号：US06503801B1

公开(公告)日：2003-01-07

申请号：US09640186

申请日：2000-08-17

Applicant: Richard P. Rouse ,  Che-Hoo Ng ,  Judy X. An

Inventor： Richard P. Rouse ,  Che-Hoo Ng ,  Judy X. An

IPC: H01L21336

CPC classification number: H01L29/66575 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/66659

Abstract: A semiconductor device with reduced leakage current is obtained by forming a non-uniform channel doping profile. A high impurity region of the opposite conductive type of a source region is formed between the channel region and source region by transient enhanced diffusion (TED). The high impurity region substantially reduces the threshold voltage rolling off problem.

Abstract translation: 通过形成不均匀的沟道掺杂分布来获得具有减小的漏电流的半导体器件。 通过瞬时增强扩散（TED）在沟道区域和源极区域之间形成相反导电类型的源极区域的高杂质区域。 高杂质区域大大降低了阈值电压下降的问题。