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公开(公告)号：US20220229752A1
公开(公告)日：2022-07-21
申请号：US17152901
申请日：2021-01-20
Applicant: STMicroelectronics International N.V.
Inventor： Avneep Kumar Goyal
IPC: G06F11/263 , G06F11/22 , G06F1/06
Abstract: An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.
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公开(公告)号：US11374580B2
公开(公告)日：2022-06-28
申请号：US17381754
申请日：2021-07-21
Applicant: STMicroelectronics International N.V.
Inventor： Sagnik Mukherjee , Ankit Gupta
Abstract: A PLL includes a phase-frequency-detector-and-charge-pump-circuit (PFDCPC) receiving a reference signal and divided signal, and generating a charge-pump current. A loop-filter is between output of the PFDCPC and a reference-voltage. A first voltage-to-current converter (V2I1) has low gain, and a second voltage-to-current converter (V2I2) has high gain. A low-gain-path is between outputs of the PFDCPC and V2I1, and a high-gain-path is between the outputs of the PFDCPC and V2I2. A current-controlled-oscillator receives an input signal, and generates an output signal. A loop divider divides the output signal by a divider-value, producing the divided signal. The low-gain-path runs directly from the PFDCPC, through the V2I1, to the input of the current-controlled-oscillator. The high-gain-path runs from the PFDCPC to the loop-filter, from a tap of the loop-filter to a low-pass filter through a current mirror, from a tap of the low-pass filter through the V2I2, to the input of the current-controlled-oscillator.
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公开(公告)号：US20220196485A1
公开(公告)日：2022-06-23
申请号：US17521123
申请日：2021-11-08
Applicant: STMicroelectronics International N.V.
Inventor： Pijush Kanti PANJA , Kallol CHATTERJEE , Atul DWIVEDI
Abstract: A temperature sensing circuit a switched capacitor circuit selectively samples ΔVbe and Vbe voltages and provides the sampled voltages to inputs of an integrator. A quantization circuit quantizes outputs of the integrator to produce a bitstream. When a most recent bit of the bitstream is a logic zero, operation includes sampling and integration of ΔVbe a first given number of times to produce a voltage proportional to absolute temperature. When the most recent bit of the bitstream is a logic one, operation includes cause sampling and integration of Vbe a second given number of times to produce a voltage complementary to absolute temperature. A low pass filter and decimator filters and decimates the bitstream produced by the quantization circuit to produce a signal indicative of a temperature of a chip into which the temperature sensing circuit is placed.
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公开(公告)号：US11360143B2
公开(公告)日：2022-06-14
申请号：US17083876
申请日：2020-10-29
Applicant: STMicroelectronics International N.V. , STMicroelectronics Application GmbH , STMicroelectronics S.r.l.
Inventor： Avneep Kumar Goyal , Deepak Baranwal , Thomas Szurmant , Nicolas Bernard Grossier
IPC: G01R31/317 , G01R31/3185 , G01R31/3193 , G06F11/34 , G01R31/319 , G06F11/36
Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.
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公开(公告)号：US11356018B2
公开(公告)日：2022-06-07
申请号：US17313533
申请日：2021-05-06
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
IPC: H02M3/07
Abstract: A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.
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Patent Agency Ranking
公开(公告)号：US11308979B2
公开(公告)日：2022-04-19
申请号：US17158817
申请日：2021-01-26
Inventor： Mahesh Chowdhary , Arun Kumar , Ghanapriya Singh , Rajendar Bahl
Abstract: A method and apparatus for classifying a spatial environment as open or enclosed are provided. In the method and apparatus, one or more microphones detect ambient sound in a spatial environment and output an audio signal representative of the ambient sound. A processor determines a spatial environment impulse response (SEIR) for the audio signal and extracts one or more features of the SEIR. The processor classifies the spatial environment as open or enclosed based on the one or more features of the SEIR.
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公开(公告)号：US20220077776A1
公开(公告)日：2022-03-10
申请号：US17016588
申请日：2020-09-10
Applicant: STMicroelectronics International N.V.
Inventor： Pravesh Kumar SAINI
Abstract: A power transistor and a cascode transistor are connected in series. A driver circuit has an output driving a control terminal of the power transistor. The driver circuit has a first power supply node coupled to receive a floating voltage that is also applied to a control terminal of the cascode transistor. A variable voltage generator generates the floating voltage. The floating voltage track either a power supply voltage or a reference voltage over a first range of voltage levels for the power supply voltage. The floating voltage further satisfies a ratio metric relationship dependent on the power supply voltage and reference voltage over a second range of voltage levels for said power supply voltage.
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公开(公告)号：US20220069837A1
公开(公告)日：2022-03-03
申请号：US17374351
申请日：2021-07-13
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
Abstract: A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.
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179.发明申请公开(公告)号：US20220029636A1
公开(公告)日：2022-01-27
申请号：US17344450
申请日：2021-06-10
Applicant: STMicroelectronics International N.V.
Inventor： Vivek TRIPATHI
Abstract: A quad signal generator circuit generates four 2N-1 bit control signals in response to a 2N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2N-1 bit control signals. Outputs of the 2N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2N-1 bit thermometer coded signal and a time delay applied to the 2N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N-1 bit thermometer coded signal.
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公开(公告)号：US11223345B2
公开(公告)日：2022-01-11
申请号：US17328525
申请日：2021-05-24
Applicant: STMicroelectronics International N.V.
Inventor： Manoj Kumar
IPC: H03K3/037
Abstract: An input signal having a logic low level at a first voltage and a logic high level at a second voltage is received by a Schmitt trigger. A voltage generator outputs a reference voltage generated from a third voltage that is higher than the second voltage. A first transistor coupled between the third voltage and a power supply node of the Schmitt trigger is biased by the reference voltage to apply a fourth voltage to the power supply node of the Schmitt trigger that is dependent on the reference voltage. The reference voltage has a value which causes the fourth voltage to be less than or equal to the second voltage. A second transistor coupled between the input signal and the input of the Schmitt trigger circuit is also biased by the reference voltage to control the logic high level voltage of the input signal at the Schmitt trigger.
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