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    Transient and stable state read operations of a memory device
    181.
    发明授权
    Transient and stable state read operations of a memory device 有权

    公开(公告)号：US12224016B2

    公开(公告)日：2025-02-11

    申请号：US17888781

    申请日：2022-08-16

    Applicant: Micron Technology, Inc.

    Inventor： Ugo Russo ,  Karan Banerjee ,  Shyam Sunder Raghunathan

    IPC: G11C16/26

    Abstract: A memory system may implement a read operation including a delay if a channel is at stable state, and may implement a read operation without a delay if the channel is in a transient state. Upon receiving a read command to a set of memory cells sharing the channel, the memory system may determine whether the channel is in a stable or transient state. If the channel is in a stable state, the memory system may perform a read operation including a delay between boosting the channel and driving respective word lines, such that the channel partially discharges prior to driving the word lines. If the channel is in a transient state, the memory system may perform a read operation without a delay between boosting the channel and driving the word lines.

    Memory-aligned access operations
    182.
    发明授权
    Memory-aligned access operations 有权

    公开(公告)号：US12223204B2

    公开(公告)日：2025-02-11

    申请号：US18080568

    申请日：2022-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Luca Porzio ,  Dionisio Minopoli ,  Olivier Duval

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for memory-aligned access operations are described. A target packet size based on a quantity of physical pages addressable by individual first-level pages of a first-level page table for mapping logical address to respective physical pages may be indicated to a host system. A buffer may be configured based on the target packet size and data for an application at the host system and associated with the target packet size may be stored in the buffer. Based on a utilization threshold of the buffer being reached, a set of data stored in the buffer and having the target packet size may be written to a memory device, where a set of physical addresses for storing the set of data may be identified based on a second-level entry of a second-level page.

    Intra-controllers for error correction code
    185.
    发明授权
    Intra-controllers for error correction code 有权

    公开(公告)号：US12222803B2

    公开(公告)日：2025-02-11

    申请号：US18216254

    申请日：2023-06-29

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  John D. Porter

    IPC: G06F11/10

    Abstract: An on-die controller can provide an error correction capability for data stored in an array of memory cells located on the same die as the on-die controller. The error correction capability provided by the on-die controller eliminates a need to transfer error correction code (ECC) data to an external controller that may have provided the error correction capability in lieu of the on-die controller, which can provide more channel bandwidth for other types of non-user data for further strengthening data reliability, security, integrity of the memory system.

    EFFICIENT FABRICATION OF MEMORY STRUCTURES
    186.
    发明申请
    EFFICIENT FABRICATION OF MEMORY STRUCTURES 有权

    公开(公告)号：US20250048652A1

    公开(公告)日：2025-02-06

    申请号：US18803145

    申请日：2024-08-13

    Applicant: Micron Technology, Inc.

    Inventor： Don Koun Lee ,  Kevin Lee Baker ,  Lei Wei

    IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

    Abstract: Methods, systems, and devices for efficient fabrication of memory structures are described. A multi-deck memory device may be fabricated using a sequence of fabrication steps that include depositing a first metal layer, depositing a cell layer on the first metal layer to form memory cells of the first memory deck, and depositing a second metal layer on the cell layer. The second metal layer may be deposited using a single deposition process rather than using multiple deposition processes. A second memory deck may be formed on the second metal layer such that stacked memory cells from the first and second deck share the use of the second metal layer. Using a single deposition process for the second metal layer may decrease the quantity of fabrication steps used to fabricate the multi-deck memory array and reduce or eliminate the exposure of the cell material to metal etchants.

    MIXED WRITE CURSOR FOR BLOCK STRIPE WRITING
    188.
    发明申请
    MIXED WRITE CURSOR FOR BLOCK STRIPE WRITING 有权

    公开(公告)号：US20250046378A1

    公开(公告)日：2025-02-06

    申请号：US18925775

    申请日：2024-10-24

    Applicant: Micron Technology, Inc.

    Inventor： Donghua ZHOU

    IPC: G11C16/10 ,  G06F3/06 ,  G06F12/02 ,  G11C16/08 ,  G11C16/16

    Abstract: Implementations described herein relate to a mixed write cursor for block stripe writing. In some implementations, a memory system may include one or more components that are configured to construct a block stripe associated with a write cursor, where the block stripe is associated with memory blocks from respective memory dies of a set of memory dies. The one or more components may be configured to program the first data to a first one or more memory blocks of the block stripe following a first logical write direction associated a logical order of the set of memory dies. The one or more components may be configured to program the second data to a second one or more memory blocks of the block stripe following a second logical write direction associated with the logical order of the set of memory dies.

    REDUNDANCY AND MAJORITY VOTING IN A KEY-VALUE DATA STORAGE SYSTEM USING CONTENT ADDRESSABLE MEMORY
    189.
    发明申请
    REDUNDANCY AND MAJORITY VOTING IN A KEY-VALUE DATA STORAGE SYSTEM USING CONTENT ADDRESSABLE MEMORY 有权

    公开(公告)号：US20250046374A1

    公开(公告)日：2025-02-06

    申请号：US18915268

    申请日：2024-10-14

    Applicant: Micron Technology, Inc.

    Inventor： Tyler L. Betz ,  Manik Advani ,  Tomoko Ogura Iwasaki ,  Violante Moschiano

    IPC: G11C15/04 ,  G11C7/10

    Abstract: A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key and identifies, from the plurality of stored search keys in the CAM block, multiple redundant copies of a stored search key that match the input search key. The processing device further determining whether a number of the multiple redundant copies of the stored search key that match the input search key satisfies a threshold criterion. Responsive to the number of the multiple redundant copies of the stored search key that match the input search key satisfying the threshold criterion, the processing device determines a match result for the input search key.

    DYNAMIC RANDOM ACCESS MEMORY SPEED BIN COMPATIBILITY
    190.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY SPEED BIN COMPATIBILITY 有权

    公开(公告)号：US20250046353A1

    公开(公告)日：2025-02-06

    申请号：US18927574

    申请日：2024-10-25

    Applicant: Micron Technology, Inc.

    Inventor： Erik V. Pohlmann

    IPC: G11C7/10 ,  G11C8/18

    Abstract: Methods, systems, and devices for dynamic random access memory speed bin compatibility are described. For instance, a device (e.g., a memory device, a host device) may combine a first parameter with a second parameter to generate a third parameter, where the first parameter may be associated with a duration for a clock that is coupled with a memory array to perform a clock cycle and the second parameter may be associated with a timing constraint associated with initiating an access operation for the memory array. The device may determine a latency of a column address strobe based on the third parameter relative to (e.g., satisfying) a threshold value and may access one or more memory cells of the memory array based on the latency of the column address strobe.

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