Control gate structures for field-effect transistors

    公开(公告)号:US11121223B2

    公开(公告)日:2021-09-14

    申请号:US16685205

    申请日:2019-11-15

    Abstract: Field-effect transistors, and apparatus including such field-effect transistors, including a gate dielectric overlying a semiconductor and a control gate overlying the gate dielectric. The control gate might include an instance of a first polycrystalline silicon-containing material containing polycrystalline silicon, and an instance of a second polycrystalline silicon-containing material containing polycrystalline silicon-germanium or polycrystalline silicon-germanium-carbon.

    CONTROL GATE STRUCTURES FOR FIELD-EFFECT TRANSISTORS

    公开(公告)号:US20210151573A1

    公开(公告)日:2021-05-20

    申请号:US16685205

    申请日:2019-11-15

    Abstract: Field-effect transistors, and apparatus including such field-effect transistors, including a gate dielectric overlying a semiconductor and a control gate overlying the gate dielectric. The control gate might include an instance of a first polycrystalline silicon-containing material containing polycrystalline silicon, and an instance of a second polycrystalline silicon-containing material containing polycrystalline silicon-germanium or polycrystalline silicon-germanium-carbon.

    Integrated Assemblies, and Methods of Forming Integrated Assemblies

    公开(公告)号:US20210125997A1

    公开(公告)日:2021-04-29

    申请号:US16666709

    申请日:2019-10-29

    Abstract: Some embodiments include an integrated assembly having an active region which contains semiconductor material. The active region includes first, second and third source/drain regions within the semiconductor material, includes a first channel region within the semiconductor material and between the first and second source/drain regions, and includes a second channel region within the semiconductor material and between the second and third source/drain regions. The semiconductor material includes at least one element selected from Group 13 of the periodic table. A digit line is electrically coupled with the second source/drain region. A first transistor gate is operatively proximate the first channel region. A second transistor gate is operatively proximate the second channel region. A first storage-element is electrically coupled with the first source/drain region. A second storage-element is electrically coupled with the third source/drain region. Some embodiments include methods of forming integrated assemblies.

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