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    Memory device having 2-transistor vertical memory cell and conductive shield structure
    2.
    发明授权
    Memory device having 2-transistor vertical memory cell and conductive shield structure 有权

    公开(公告)号：US12213321B2

    公开(公告)日：2025-01-28

    申请号：US17515065

    申请日：2021-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Richard E. Fackenthal ,  Durai Vishak Nirmal Ramaswamy

    IPC: H10B43/50 ,  H01L21/28 ,  H01L29/10

    Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first memory cell including a first transistor including a first channel region and a first charge storage structure, and a second transistor including a second channel region formed over the charge storage structure; a second memory cell adjacent the first memory cell, the second memory cell including a third transistor including a third channel region and a second charge storage structure, and a fourth transistor including a fourth channel region formed over the second charge storage structure; a first access line adjacent a side of the first memory cell; a second access line adjacent a side of the second memory cell; a first dielectric material adjacent the first channel region; a second dielectric material adjacent the third channel region; and a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials.

    MEMORY DEVICE HAVING SHARED ACCESS LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELL
    3.
    发明申请
    MEMORY DEVICE HAVING SHARED ACCESS LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELL 有权

    公开(公告)号：US20240414911A1

    公开(公告)日：2024-12-12

    申请号：US18808256

    申请日：2024-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

    IPC: H10B12/00

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

    Memory Circuitry And Methods Used In Forming Memory Circuitry
    4.
    发明公开
    Memory Circuitry And Methods Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240315001A1

    公开(公告)日：2024-09-19

    申请号：US18598585

    申请日：2024-03-07

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  David Daycock ,  Albert Liao ,  Si-Woo Lee ,  Haitao Liu

    IPC: H10B12/00

    CPC classification number: H10B12/30 ,  H10B12/05

    Abstract: Memory circuitry comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprising a transistor comprise a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A gate is operatively-proximate the channel region. A capacitor comprises a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes. The first capacitor electrode is directly electrically coupled to the first source/drain region. The second capacitor electrode of multiple of the capacitors is directly electrically coupled with one another. Digitlines extend elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory-cell tiers are directly electrically coupled to individual of the digitlines. A wordline is in individual of the memory-cell tiers that comprises the gate of multiple of the individual transistors in the individual memory-cell tiers. The wordline in a lower of the memory-cell tiers has a greater minimum width than a minimum width of the wordline in a higher of the memory-cell tiers that is directly above the lower memory-cell tier. Methods are also disclosed.

    Memory device having 2-transistor vertical memory cell and shield structures
    8.
    发明授权
    Memory device having 2-transistor vertical memory cell and shield structures 有权

    公开(公告)号：US11950402B2

    公开(公告)日：2024-04-02

    申请号：US18137852

    申请日：2023-04-21

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L29/24 ,  G11C5/06 ,  H10B12/00

    CPC classification number: H10B12/20 ,  G11C5/063 ,  H01L29/24 ,  H10B12/01

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is located between and electrically separated from the first and second charge storage structures. The conductive line forms a gate of each of the first, second, third, and fourth transistors.

    TRANSISTORS WITH MITIGATED FREE BODY EFFECT
    10.
    发明公开
    TRANSISTORS WITH MITIGATED FREE BODY EFFECT 审中-公开

    公开(公告)号：US20240072174A1

    公开(公告)日：2024-02-29

    申请号：US18237206

    申请日：2023-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Anthony J. Kanago ,  Haitao Liu ,  Si-Woo Lee ,  Soichi Sugiura

    IPC: H01L29/786 ,  H10B12/00

    CPC classification number: H01L29/78615 ,  H01L29/78642 ,  H10B12/05 ,  H10B12/315

    Abstract: A variety of applications can include an apparatus having an electronic device including a number of transistors in a pair-wise arrangement that can address a floating body effect associated with the type of transistor implemented in the pair-wise arrangement. The transistors can be structured as thin film transistors having one-gate separated by a gate dielectric from a vertical channel structure. The pair-wise arrangement can include a conductive shield between a channel structure of a transistor of the pair and a channel structure of the other transistor of the other pair. A conductive body can be located below the conductive shield and shorted to the conductive shield, where the conductive body contacts the channel structures of the transistors of the pair-wise arrangement. The conductive shield can be coupled to node to be set at a constant voltage in operation.

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