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    Memory device having memory cell strings and separate read and write control gates
    2.
    发明授权
    Memory device having memory cell strings and separate read and write control gates 有权

    公开(公告)号：US12200928B2

    公开(公告)日：2025-01-14

    申请号：US17387669

    申请日：2021-07-28

    Applicant: Micron Technology, Inc.

    Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin ,  Yingda Dong

    IPC: H10B43/27 ,  H01L21/28 ,  H01L29/423 ,  H10B41/27

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES
    3.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES 有权

    公开(公告)号：US20240420750A1

    公开(公告)日：2024-12-19

    申请号：US18818295

    申请日：2024-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E. Fackenthal ,  Duane R. Mills

    IPC: G11C11/404

    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

    TWO TRANSISTOR CELLS FOR VERTICAL THREE-DIMENSIONAL MEMORY HAVING VERICAL DIGIT LINES
    4.
    发明公开
    TWO TRANSISTOR CELLS FOR VERTICAL THREE-DIMENSIONAL MEMORY HAVING VERICAL DIGIT LINES 审中-公开

    公开(公告)号：US20240357794A1

    公开(公告)日：2024-10-24

    申请号：US18645043

    申请日：2024-04-24

    Applicant: Micron Technology, Inc.

    Inventor： Litao Yang ,  Haitao Liu ,  Kamal M. Karda ,  Si-Woo Lee

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: Systems, methods and apparatus are provided for two transistor cells for vertical three-dimensional memory. The memory has pairs of serially connected transistors, each pair of serially connected transistors having an independent first source/drain region and a shared second source/drain region separated by channel regions; horizontally oriented access lines separated from the channel regions by a gate dielectric material; and vertically oriented digit lines electrically coupled to the first source/drain regions of the serially connected transistors.

    Memory device having shared access line for 2-transistor vertical memory cell
    6.
    发明授权
    Memory device having shared access line for 2-transistor vertical memory cell 有权

    公开(公告)号：US12069853B2

    公开(公告)日：2024-08-20

    申请号：US17712674

    申请日：2022-04-04

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

    IPC: H10B12/00

    CPC classification number: H10B12/50 ,  H10B12/01

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

    MEMORY DEVICE HAVING TIERS OF MEMORY CELLS AND ACCESS LINE HAVING MULTIPLE CONDUCTIVE REGIONS
    7.
    发明公开
    MEMORY DEVICE HAVING TIERS OF MEMORY CELLS AND ACCESS LINE HAVING MULTIPLE CONDUCTIVE REGIONS 审中-公开

    公开(公告)号：US20240274194A1

    公开(公告)日：2024-08-15

    申请号：US18435434

    申请日：2024-02-07

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu

    IPC: G11C16/04 ,  G11C5/06 ,  H10B41/27

    CPC classification number: G11C16/0483 ,  G11C5/063 ,  H10B41/27

    Abstract: Some embodiments include apparatuses in which one of the apparatuses includes a first conductive structure, a second conductive structure, a third conductive structure, and a memory cell. The memory cell includes a semiconductor portion located on a first level of the apparatus and coupled to the first conductive structure, and a charge storage structure located on the first level coupled to the semiconductor portion and separated from the second conductive structure. The third conductive structure is located on a second level of the apparatus adjacent the semiconductor portion, and including first, second, and third conductive regions. The third conductive region is located between the first and second conductive regions and has a material different from a material of the first conductive region and a material of the second conductive region.

    MEMORY DEVICE HAVING TIERS OF 2-TRANSISTOR MEMORY CELLS
    9.
    发明公开
    MEMORY DEVICE HAVING TIERS OF 2-TRANSISTOR MEMORY CELLS 审中-公开

    公开(公告)号：US20240188273A1

    公开(公告)日：2024-06-06

    申请号：US18521273

    申请日：2023-11-28

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Karthik Sarpatwari

    IPC: H10B12/00 ,  G11C11/405 ,  G11C11/4096

    CPC classification number: H10B12/00 ,  G11C11/405 ,  G11C11/4096

    Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes first, second, and third conductive structures, each having a length in a first direction, first and second memory cells spaced apart from each other in a second direction perpendicular to the first direction, first conductive regions, and second conductive regions. Each of the first and second memory cells includes a first semiconductor portion located on a first level of the apparatus and coupled to the third conductive structure and one of the first and second conductive structures, a second semiconductor portion located on a second level of the apparatus and coupled to one of the first and second conductive structures. The first conductive regions are opposite the first and second semiconductor portions, respectively, of the first memory cell. Second conductive regions are opposite the first and second semiconductor portions, respectively, of the second memory cell.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATE
    10.
    发明公开
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATE 审中-公开

    公开(公告)号：US20240047356A1

    公开(公告)日：2024-02-08

    申请号：US18234602

    申请日：2023-08-16

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L23/528 ,  H01L29/24 ,  G11C5/06 ,  H10B12/00

    CPC classification number: H01L23/5286 ,  H01L29/24 ,  G11C5/063 ,  H10B12/01 ,  H10B12/20

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a data line, a memory cell coupled to the data line, a ground connection, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the data line, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The ground connection is coupled to the first region of the first transistor. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

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