公开(公告)号：US20240029778A1

公开(公告)日：2024-01-25

申请号：US17871752

申请日：2022-07-22

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G11C11/406

CPC classification number: G11C11/40618

Abstract: In various examples, refreshing a bank can include receiving a refresh command, wherein the refresh command comprises selector bits and receiving mode register bits from the mode registers. Refreshing a bank can also include refreshing a number of banks from the plurality of banks utilizing the mode register bits and the selector bits.

公开(公告)号：US11830575B2

公开(公告)日：2023-11-28

申请号：US17805264

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim

IPC: G11C7/10 ,  G11C8/10 ,  G11C8/18

CPC classification number: G11C7/1084 ,  G11C7/106 ,  G11C7/1057 ,  G11C7/1087 ,  G11C8/10 ,  G11C8/18

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

公开(公告)号：US20230307030A1

公开(公告)日：2023-09-28

申请号：US17656801

申请日：2022-03-28

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4085 ,  G11C11/4076

Abstract: Described apparatuses and methods relate to adaptive wordline refresh for a memory system that may support a nondeterministic protocol. To help manage power delivery networks in a memory system, a memory device can include logic that can stagger activation of multiple wordlines that are to be activated or refreshed approximately simultaneously. The logic circuitry can be coupled between wordlines that are to be activated and delay propagation of the activation signal. Thus, a first group of wordlines (e.g., “before” the logic circuitry) are activated by the signal, but activation of a second group of wordlines (e.g., “after” the logic circuitry), is delayed, reducing the peak current draw. Additional logic circuitries can be coupled between the wordlines to divide the wordlines into multiple groups, thereby staggering the activation of wordlines that are activated by a refresh command, which can reduce the peak current draw and power consumption.

公开(公告)号：US11747992B2

公开(公告)日：2023-09-05

申请号：US17349634

申请日：2021-06-16

Applicant: Micron Technology, Inc.

Inventor： Saira Samar Malik ,  Hyunyoo Lee ,  Chinnakrishnan Ballapuram ,  Taeksang Song ,  Kang-Yong Kim

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7211

Abstract: Methods, systems, and devices for memory wear management are described. A device may include an interface controller and a non-volatile memory. The interface controller may manage wear-leveling procedures for memory banks in the non-volatile memory. For example, the interface controller may select a row in a memory bank for the wear-leveling procedure. The interface controller may store data from the row in a buffer in the interface controller. The interface controller may then transfer the data to the non-volatile memory so that the non-volatile memory can write the data to a second row of the memory bank.

公开(公告)号：US20230236731A1

公开(公告)日：2023-07-27

申请号：US17940789

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yuan He ,  Kang-Yong Kim

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0673 ,  G06F3/0659

Abstract: A dynamic random access memory employs either or both of a normal row copy operation or a fast row copy operation to copy selected data from a first row of memory to a second row of memory, without transferring the data to an intermediary processor such as a central processing unit or a memory controller. Both operations depend on a concurrent electrical activation of two separate wordlines within a bank of a DRAM. For the fast row copy operation, the two separate wordlines are part of a shared section of a DRAM bank, having shared bitlines. Bit values are copied directly in parallel via common bitlines. For the normal row copy operation, the two separate wordlines are part of a common bank but not a shared section. Bit values are copied in serial via a general input/output bus within the bank.

公开(公告)号：US11587633B2

公开(公告)日：2023-02-21

申请号：US17349612

申请日：2021-06-16

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Hyunyoo Lee ,  Saira Samar Malik ,  Kang-Yong Kim

IPC: G11C29/10 ,  G11C29/36 ,  G11C29/14 ,  G11C29/18 ,  G11C29/12

Abstract: Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.

公开(公告)号：US20220398042A1

公开(公告)日：2022-12-15

申请号：US17586534

申请日：2022-01-27

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Hyunyoo Lee ,  Kang-Yong Kim

IPC: G06F3/06

Abstract: Methods, systems, and devices for managing address access information are described. A device may receive a command for an address of a memory array. Based on or in response to the command, the device may read a first set of tag bits from the memory array. The first set of tag bits may indicate access information for a set of addresses that includes the address. The device may determine a second set of tag bits based on the command and the address. The second set of tag bits may indicate updated access information for the address. The device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.

公开(公告)号：US20220343963A1

公开(公告)日：2022-10-27

申请号：US17302206

申请日：2021-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  Sourabh Dhir ,  Keun Soo Song

IPC: G11C11/4074 ,  G11C5/14

Abstract: In some examples, memory die may include a selection pad, which may be coupled to a power potential. The selection pad may provide a signal to a selection control circuit, which may control a selection circuit to couple a power pad to one of multiple power rails. In some examples, a power management integrated circuit may include a selection circuit to provide one power potential to a package including a memory die when a selection signal has a logic level and another power potential when the selection signal has another logic level.

公开(公告)号：US20220300370A1

公开(公告)日：2022-09-22

申请号：US17654354

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F11/10 ,  G06F3/06

Abstract: Described apparatuses and methods provide configurable error correction code (ECC) circuitry and schemes that can utilize a shared ECC engine between multiple memory banks of a memory, including a low-power double data rate (LPDDR) memory. A memory device may include one or more dies with multiple memory banks. The configurable ECC circuitry can use an ECC engine that services a memory bank by producing ECC values based on data stored in the memory bank when data-masking functionality is enabled. When data-masking functionality is disabled, the configurable ECC circuitry can use the shared ECC engine that services at least two memory banks by producing ECC values with a larger quantity of bits based on respective data stored in the at least two memory banks. By using the shared ECC engine responsive to the data-masking functionality being disabled, the ECC functionality can provide higher data reliability with lower die area utilization.

公开(公告)号：US20220293146A1

公开(公告)日：2022-09-15

申请号：US17805275

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim

IPC: G11C7/10 ,  G11C8/10 ,  G11C8/18

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.