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181.发明申请公开(公告)号：US20220029636A1
公开(公告)日：2022-01-27
申请号：US17344450
申请日：2021-06-10
Applicant: STMicroelectronics International N.V.
Inventor： Vivek TRIPATHI
Abstract: A quad signal generator circuit generates four 2N-1 bit control signals in response to a 2N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2N-1 bit control signals. Outputs of the 2N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2N-1 bit thermometer coded signal and a time delay applied to the 2N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N-1 bit thermometer coded signal.
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公开(公告)号：US11223345B2
公开(公告)日：2022-01-11
申请号：US17328525
申请日：2021-05-24
Applicant: STMicroelectronics International N.V.
Inventor： Manoj Kumar
IPC: H03K3/037
Abstract: An input signal having a logic low level at a first voltage and a logic high level at a second voltage is received by a Schmitt trigger. A voltage generator outputs a reference voltage generated from a third voltage that is higher than the second voltage. A first transistor coupled between the third voltage and a power supply node of the Schmitt trigger is biased by the reference voltage to apply a fourth voltage to the power supply node of the Schmitt trigger that is dependent on the reference voltage. The reference voltage has a value which causes the fourth voltage to be less than or equal to the second voltage. A second transistor coupled between the input signal and the input of the Schmitt trigger circuit is also biased by the reference voltage to control the logic high level voltage of the input signal at the Schmitt trigger.
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公开(公告)号：US20210390180A1
公开(公告)日：2021-12-16
申请号：US17340164
申请日：2021-06-07
Inventor： Asif Rashid Zargar , Gilles Eyzat , Charul Jain
IPC: G06F21/55
Abstract: A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.
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184.发明授权公开(公告)号：US11195576B2
公开(公告)日：2021-12-07
申请号：US16596989
申请日：2019-10-09
Applicant: STMicroelectronics International N.V.
Inventor： Shishir Kumar , Bhupender Singh
IPC: G11C11/419 , G11C11/417
Abstract: A sense amplifier enable signal and a tracking signal are generated in response to an indication that a sufficient voltage difference has developed across bit lines of a memory. The sense amplifier enable signal has a pulse width between a leading edge and a trailing edge. The sense amplifier enable signal is propagated along a first U-turn signal line that extends parallel to rows of the memory array and is coupled to sense amplifiers arranged in a row to generate a sense amplifier enable return signal. The tracking signal is propagated along a second U-turn signal line extending parallel to columns of the memory array to generate a tracking return signal. The sense amplifier enable return signal and the tracking return signal are logically combined to generate a reset signal. Timing of the trailing edge of the pulse width is controlled by the reset signal.
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公开(公告)号：US20210375787A1
公开(公告)日：2021-12-02
申请号：US17322712
申请日：2021-05-17
Inventor： Paolo CREMA , Jürgen BARTHELMES , Din-Ghee NEOH
Abstract: The present disclosure is directed to a lead frame design that includes a copper alloy base material coated with an electroplated copper layer, a precious metal, and an adhesion promotion compound. The layers compensate for scratches or surface irregularities in the base material while promoting adhesion from the lead frame to the conductive connectors, and to the encapsulant by coupling them to different layers of a multilayer coating on the lead frame. The first layer of the multilayer coating is a soft electroplated copper to smooth the surface of the base material. The second layer of the multilayer coating is a thin precious metal to facilitate a mechanical coupling between leads of the lead frame and conductive connectors. The third layer of the multilayer coating is the adhesion promotion compound for facilitating a mechanical coupling to an encapsulant around the lead frame.
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Patent Agency Ranking
公开(公告)号：US20210294534A1
公开(公告)日：2021-09-23
申请号：US17341054
申请日：2021-06-07
Inventor： Roberto Colombo , Om Ranjan
Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration data client.
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公开(公告)号：US11119153B1
公开(公告)日：2021-09-14
申请号：US16888059
申请日：2020-05-29
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan
IPC: G01R31/3177 , G01R31/3185 , G01R31/317 , G01R31/28
Abstract: A method of testing a multiple power domain device includes sending a control signal from a test controller powered by a switchable power domain to a non-scan test data register powered by an always on power domain. The method further includes setting, using the control signal, a test data register value of the register to enable scan mode by bypassing an isolation cell between an output of the switchable domain and an input of the always on domain and, while the register value continuously enables scan mode: shifting a test pattern into a scan chain including a flip-flop coupled to the isolation cell, capturing a test result from the scan chain, and shifting the test pattern out of the scan chain to observe the test result. The isolation cell is configured to allow or disallow propagation of a signal from the output to the input.
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公开(公告)号：US20210281172A1
公开(公告)日：2021-09-09
申请号：US17313533
申请日：2021-05-06
Applicant: STMicroelectronics International N.V.
Inventor： Vikas RANA
IPC: H02M3/07
Abstract: A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.
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公开(公告)号：US20210265947A1
公开(公告)日：2021-08-26
申请号：US17175732
申请日：2021-02-15
Applicant: STMicroelectronics International N.V.
Inventor： Gagan MIDHA , Anurup MITRA , Kallol CHATTERJEE
Abstract: Disclosed herein is a fine capacitance tuning circuit for a digitally controlled oscillator. The tuning circuit has low and high frequency tuning banks formed by varactors that have their top plates connected to one another. A controller initially sets states of switches selectively connecting the bottom plates of the varactors of the low frequency bank to a low voltage, a high voltage, or to an RC filter, in response to an integer portion of a control word. A sigma-delta modulator initially sets the states of switches selectively connecting the bottom plates of the varactors of the high frequency bank to either the low voltage or the high voltage, in response to a fractional portion of the control word. The controller modifies the states of the switches of the tuning banks in a complementary fashion, based upon comparisons between the fractional portion of the control word and a series of thresholds.
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公开(公告)号：US11102617B2
公开(公告)日：2021-08-24
申请号：US16743854
申请日：2020-01-15
Applicant: STMicroelectronics International N.V.
Inventor： Jitendra Jain , Alok Kumar Mittal
Abstract: This application discloses systems, devices, and methods for indoor navigation and tracking with a mesh network. In one aspect, a navigation device includes a receiver configured to receive a locational signal from a node network. The locational signal identifies a respective node of the node network, and the node network is distributed throughout a physical space. The navigation device includes a memory storing a program and a processor in communication with the receiver and configured to execute the program to calculate a position of the navigation device from the identity of the respective node, determine a routing instruction from the position of the navigation device to a destination based on the position of the navigation device and a known mapping of the node network in the physical space, and update the position of the navigation device and the routing instruction as the navigation device moves through the physical space.
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