公开(公告)号：US07821345B2

公开(公告)日：2010-10-26

申请号：US11656900

申请日：2007-01-23

Applicant: Michael Kraemer ,  Sebastien Rieubon

Inventor： Michael Kraemer ,  Sebastien Rieubon

IPC: H03L7/00

CPC classification number: H03L7/087 ,  H03L7/10 ,  H03L2207/06

Abstract: A method of calibrating an oscillator in order to compensate the dispersions generated, on the one hand, during the process of fabricating the oscillator circuit components and, on the other hand, by variations of operating conditions by modifying the parameters of a resonant component, for example a capacitor or an induction coil of the oscillator, in order to change the frequency range covered by the oscillator, according to the control voltage. Accordingly, calibrating the oscillator adjusts the output frequency of the oscillator according to an oscillator control signal. The calibration device determines the difference between the output frequency of the oscillator divided by a quantity and a reference frequency of the oscillator. The device includes a set of impedances selectively connected to the oscillator and each corresponding to a frequency deviation of the oscillator, and a calibration stage to generate a calibration word according to the measured frequency difference.

Abstract translation: 一种校准振荡器的方法，一方面是在制造振荡器电路部件的过程中补偿所产生的分散，另一方面，通过修改共振分量的参数，通过改变工作条件，为了 例如振荡器的电容器或感应线圈，以便根据控制电压改变振荡器覆盖的频率范围。 因此，校准振荡器根据振荡器控制信号来调节振荡器的输出频率。 校准装置确定振荡器的输出频率除以振荡器的参考频率之间的差异。 该装置包括一组阻抗，其选择性地连接到振荡器，并且每一个对应于振荡器的频率偏差，以及校准阶段，以根据测量的频率差产生校准字。

公开(公告)号：US07804383B2

公开(公告)日：2010-09-28

申请号：US11845268

申请日：2007-08-27

Applicant: Alexandre Volatier ,  Pascal Ancey ,  Bertrand Dubus

Inventor： Alexandre Volatier ,  Pascal Ancey ,  Bertrand Dubus

IPC: H03H9/54 ,  H03H9/56

CPC classification number: H03H9/02228 ,  Y10T29/42

Abstract: A coupled Lamb wave resonator filter includes first and second Lamb wave resonators. The first Lamb wave resonator includes a first resonant layer, and first and second electrodes on opposite sides of the first resonant layer. The second Lamb wave resonator includes a second resonant layer, and third and fourth electrodes on opposite sides of the second resonant layer. One of the sides of the first resonant layer belongs to a plane parallel to a plane corresponding to one of the sides of the second resonant layer. Both planes pass through the third and fourth electrodes of the second Lamb wave resonator. A periodic lattice acoustically couples the first and second resonant layers.

Abstract translation: 耦合兰姆波谐振滤波器包括第一和第二兰姆波谐振器。 第一兰姆波谐振器包括第一谐振层，以及在第一谐振层的相对侧上的第一和第二电极。 第二兰姆波谐振器包括第二谐振层，第二谐振层的相对侧上的第三和第四电极。 第一共振层的一个侧面属于平行于与第二共振层的一个侧面相对应的平面的平面。 两个平面通过第二兰姆波谐振器的第三和第四电极。 周期性晶格声耦合第一和第二谐振层。

公开(公告)号：US07788506B2

公开(公告)日：2010-08-31

申请号：US11482511

申请日：2006-07-07

Applicant: Frédéric Bancel ,  Nicolas Berard

Inventor： Frédéric Bancel ,  Nicolas Berard

IPC: G06F11/30 ,  G11C29/04 ,  G06F11/00

CPC classification number: G06F21/79 ,  G06F21/64

Abstract: A method secures a memory in which individually read-accessible binary words are saved. The method includes defining a memory zone covering a plurality of words, calculating a cumulative signature according to all of the words in the memory zone, and storing the cumulative signature as an expected signature of the memory zone to check the integrity of data read in the memory. The method can be applied to the securing of smart cards.

Abstract translation: 一种方法可保护其中保存单独可读取的二进制字的存储器。 该方法包括定义覆盖多个单词的存储器区域，根据存储器区域中的所有单词计算累积签名，并将累积签名存储为存储器区域的期望签名，以检查在该存储区域中读取的数据的完整性 记忆。 该方法可应用于智能卡的固定。

公开(公告)号：US07755960B2

公开(公告)日：2010-07-13

申请号：US12333426

申请日：2008-12-12

Applicant: Bertrand Borot ,  Emmanuel Bechet

Inventor： Bertrand Borot ,  Emmanuel Bechet

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C29/24 ,  G11C29/50012

Abstract: A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells.

Abstract translation: 存储器包括多个存储单元，每个存储单元包括连接到真位线的真实数据输入和连接到互补位线的互补数据输入，以及两个逆变器，其首先连接到真实数据输入端，其次是至 补充数据输入。 存储器还包括测试电路，其包括多个测试单元，每个测试单元包括连接到前一测试单元的互补数据输入端的真实数据输入端和连接到以下测试单元的真实数据输入端的互补数据输入端， 最后一个测试单元的互补数据输入被连接到第一测试单元的真实数据输入，每个测试单元包括连接在真实数据输入和互补数据输入之间的第一反相器。 如此形成的环形链传播其周期是存储单元的性能的函数的信号。

公开(公告)号：US07714622B2

公开(公告)日：2010-05-11

申请号：US11624135

申请日：2007-01-17

Applicant: Francois Tailliet

Inventor： Francois Tailliet

IPC: H03K5/153

CPC classification number: H03K5/086

Abstract: An input stage of an integrated circuit, includes a comparator for comparing the voltage of an input signal of the input stage with a reference voltage, and supplying a binary output signal the value of which depends on the result of the comparison of the input signal with the reference voltage. The input stage comprises a feedback circuit measuring a parameter representative of the operation of the comparator, and raising the reference voltage while the measured parameter reveals a faulty operation of the comparator.

Abstract translation: 集成电路的输入级包括比较器，用于将输入级的输入信号的电压与参考电压进行比较，并提供二进制输出信号，该二进制输出信号的值取决于输入信号的比较结果与 参考电压。 输入级包括测量表示比较器的操作的参数的反馈电路，以及提高参考电压，而测量的参数显示比较器的故障操作。

公开(公告)号：US07710699B2

公开(公告)日：2010-05-04

申请号：US11014520

申请日：2004-12-14

Applicant: Arnaud Florence ,  Jérome Heurtier ,  Franck Galtie

Inventor： Arnaud Florence ,  Jérome Heurtier ,  Franck Galtie

IPC: H02H3/08

CPC classification number: H02H9/02 ,  H02M1/32 ,  H02M3/156

Abstract: A method and a circuit for limiting the current in an inductance, comprising means for interrupting the power storage in the inductance at the end of a delay triggered by the current in the inductance.

Abstract translation: 一种用于限制电感中的电流的方法和电路，包括用于在由电感中的电流触发的延迟结束时中断电感中的功率存储的装置。

公开(公告)号：US07679945B2

公开(公告)日：2010-03-16

申请号：US12043766

申请日：2008-03-06

Applicant: Pierre Rizzo ,  Christophe Moreaux ,  David Naura ,  Ahmed Kari

Inventor： Pierre Rizzo ,  Christophe Moreaux ,  David Naura ,  Ahmed Kari

IPC: G11C11/24

CPC classification number: G11C11/4023 ,  G06K7/10029 ,  G06K7/10059 ,  G06K19/07749

Abstract: A persistent volatile memory cell memorizes a binary datum during a retention time independent from a supply voltage of the memory cell. The memory cell comprises a capacitive memory point supplying a persistent voltage and having a determined discharge time, a switch for triggering the discharge of the memory point when an erase signal has an active value, a switch for triggering the charge of the memory point when a write signal has an active value, and a sense-amplifier circuit having an input receiving the persistent voltage, and an output supplying the binary datum. The memory cell can be applied to the management of an inventory flag in a contactless integrated circuit.

Abstract translation: 永久性易失性存储器单元在独立于存储器单元的电源电压的保持时间期间存储二进制数据。 存储单元包括提供持续电压并具有确定的放电时间的电容性存储器点，当擦除信号具有有效值时用于触发存储点放电的开关，当触发存储点的充电时，当a 写信号具有有效值，以及具有接收持续电压的输入的读出放大器电路和提供二进制数据的输出。 存储单元可应用于无接触集成电路中的库存标志的管理。

公开(公告)号：US07676717B2

公开(公告)日：2010-03-09

申请号：US11673911

申请日：2007-02-12

Applicant: Frédéric Bancel ,  David Hely

Inventor： Frédéric Bancel ,  David Hely

IPC: G01R31/28

CPC classification number: G01R31/318536 ,  G01R31/31719

Abstract: An electronic circuit includes configurable cells with a test input and an output. The configurable cells are capable of being connected to one another in a chain in a predefined order via the test inputs and the outputs to form a test shift register if they receive a chaining command signal. A connection control module disconnects the test input from at least one configurable cell if the connection control module receives an invalid identification key. The connection control module leaves disconnected the test input from the at least one configurable cell, or applies a constant potential on the test input of the at least one configurable cell, or connects the test input of the at least one configurable cell at an output of a random-data generator.

Abstract translation: 电子电路包括具有测试输入和输出的可配置单元。 可配置单元能够经由测试输入和输出以预定义的顺序彼此连接，以形成测试移位寄存器，如果它们接收到链接命令信号。 如果连接控制模块接收到无效的识别密钥，则连接控制模块将测试输入与至少一个可配置单元断开连接。 连接控制模块将测试输入从至少一个可配置单元断开，或者在至少一个可配置单元的测试输入上施加恒定电位，或将至少一个可配置单元的测试输入连接到 随机数据生成器。

公开(公告)号：US07676642B2

公开(公告)日：2010-03-09

申请号：US11696863

申请日：2007-04-05

Applicant: Philippe Ganivet ,  Laurent Murillo

Inventor： Philippe Ganivet ,  Laurent Murillo

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F15/177 ,  G06F9/00 ,  G06F9/24

CPC classification number: G11C7/20

Abstract: A method for initializing a control device of a memory, the control device executing commands for accessing the memory transmitted to the memory by a control signal, the method comprising steps of detecting the switching on of the memory and of at least partially initializing the control device following the switching on of the memory. According to one embodiment of the present invention, the method comprises steps of detecting a specific event in the control signal, and of at least partially initializing the control device following the detection of the specific event.

Abstract translation: 一种用于初始化存储器的控制装置的方法，所述控制装置执行用于通过控制信号访问发送到存储器的存储器的命令，所述方法包括以下步骤：检测存储器的接通和至少部分地初始化控制装置 在接通存储器之后。 根据本发明的一个实施例，该方法包括以下步骤：检测控制信号中的特定事件，以及在检测到特定事件之后至少部分地初始化控制装置。

公开(公告)号：US20100027174A1

公开(公告)日：2010-02-04

申请号：US12506477

申请日：2009-07-21

Applicant: Philippe Galy ,  Christophe Entringer ,  Alexandre Dray

Inventor： Philippe Galy ,  Christophe Entringer ,  Alexandre Dray

IPC: H02H9/04 ,  H01L23/60

CPC classification number: H01L27/0262 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/747

Abstract: The integrated circuit may include at least one electronic protection circuit for protecting against at least one electrostatic discharge and being able to discharge the overvoltage current generated by the electrostatic discharge. The electronic protection circuit includes a controlled short-circuiting switch embodied in CMOS technology including a CMOS technology TRIAC or a CMOS technology thyristor arranged in anti-parallel with a CMOS technology diode, and a triggering circuit for controlling the short-circuiting switch.

Abstract translation: 集成电路可以包括至少一个电子保护电路，用于防止至少一个静电放电并且能够放电由静电放电产生的过电压电流。 电子保护电路包括具有CMOS技术的受控短路开关，包括与CMOS技术二极管反并联布置的CMOS技术TRIAC或CMOS技术晶闸管，以及用于控制短路开关的触发电路。