-
公开(公告)号：US20220101508A1
公开(公告)日：2022-03-31
申请号：US17035729
申请日：2020-09-29
发明人： Wai Kai Arvin TANG , Pak Kan WONG
摘要： The present invention provides an anomaly detection method and apparatus based on a neural network which can be trained on undamaged normal vehicle images and able to detect unknown/unseen vehicle damages of stochastic types and extents from images which are taken in various contexts. The provided method and apparatus are implemented with functional units which are trained to perform the anomaly detection under a GCAN model with a training dataset containing images of undamaged vehicles, intact-vehicle frame images and augmented vehicle frame images of the vehicles.
-
公开(公告)号：US11269203B2
公开(公告)日：2022-03-08
申请号：US16750087
申请日：2020-01-23
摘要： Polarization-independent focusing is advantageously achieved by a multifocal system having a polarization beam splitter (PBS) to split an unpolarized light beam into two orthogonally linearly-polarized (LP) light beams. The two LP light beams are reflected by mirrors to travel in opposite directions and enter into a variable-focusing module at two ends thereof, respectively. The module includes waveplates to convert the LP light beams into two circularly-polarized (CP) light beams at both ends of an optical assembly. The optical assembly is formed with a stack of birefringent optical elements including at least one geometric phase lens and one polarization selector that may be electrically modulated to select the optical power in focusing the two CP light beams. Followed by the waveplates converting two focused CP light beams to two focused LP light beams and upon mirror reflection, the beams are finally recombined by the PBS to form one focused light beam.
-
公开(公告)号：US11176447B2
公开(公告)日：2021-11-16
申请号：US16011787
申请日：2018-06-19
摘要： A deep neural network models semiconductor devices. Measurements of test transistors are gathered into training data including gate and drain voltages and transistor width and length, and target data such as the drain current measured under the input conditions. The training data is converted by an input pre-processor that can apply logarithms of the inputs or perform a Principal Component Analysis (PCA). Rather than use measured drain current as the target when training the deep neural network, a target transformer transforms the drain current into a transformed drain current, such as a derivative of the drain current with respect to gate or drain voltages, or a logarithm of the derivative. Weights in the deep neural network are adjusted during training by comparing the deep neural network's output to the transformed drain current and generating a loss function that is minimized over the training data.
-
公开(公告)号：US11127524B2
公开(公告)日：2021-09-21
申请号：US16219982
申请日：2018-12-14
发明人： Xiaoyong Hu , Ziyang Gao , Zhou Li
摘要： An assembly for power converting includes a circuit board, a power switching circuit mounted on the circuit board, an inductor coil that includes a winding and two ends, a magnetic core that is surrounded by the winding of the inductor coil, and a magnetic mixture that encapsulates the circuit board, the power switching circuit, the inductor coil and the magnetic core. The winding of the inductor coil is stacked above the power switching circuit and is sufficiently large to fill up a size of the assembly.
-
15.发明授权公开(公告)号：US10983262B2
公开(公告)日：2021-04-20
申请号：US16136371
申请日：2018-09-20
发明人： Ming Wai Alwin Tam , Xiuling Zhu , Kin Lung Chan
摘要： A rotational geometric phase hologram has geometric phase optical elements (GPOEs) serially cascaded along a common optical axis to form a GPOE cascade used for receiving a linearly-polarized light beam and generating output light beams at an exit surface of the last GPOE. Interference occurred in the output light beams creates a polarization interference pattern on the exit surface. A photoalignment substrate, when positioned in close proximity to the exit surface, records the pattern. Advantageously, each GPOE is rotatable about the common optical axis. Respective rotation angles of the GPOEs are determined according to a spatially-varying linear polarization orientation distribution selected to be generated for the polarization interference pattern. Particularly, the respective rotation angles are reconfigurable to provide the periodicity required for the spatially-varying linear polarization orientation distribution over a range of allowed periodicities while keeping the periodicity of spatially-varying optic axis orientation distribution of each GPOE to be fixed.
-
公开(公告)号：US10862427B1
公开(公告)日：2020-12-08
申请号：US16857804
申请日：2020-04-24
发明人： Tat Fu Chan
摘要： A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.
-
17.发明授权公开(公告)号：US10777689B1
公开(公告)日：2020-09-15
申请号：US16657376
申请日：2019-10-18
发明人： Shu Kin Yau , Siu Wai Wong
摘要： A shielded Schottky heterojunction power transistor is made from a Silicon-Carbide (SiC) wafer with SiC epitaxial layers including a N+ source and a Silicon N-epitaxial layer under the gate with higher channel mobility than SiC. The bulk of the wafer is a N+ SiC drain contacted by backside metal. A trench is formed between heterojunction transistors. Metal contacting the N+ source is extended into the trench to form a Schottky diode with the N-SiC substrate. P+ taps on the sides of the trench connect the metal to a P-SiC body diode under the heterojunction gate, and also prevent the Schottky metal from directly contacting the P body diode. Buried P pillars with P+ pillar caps are formed under the trench Schottky diode and under the heterojunction transistors. The P pillars provide shielding by balancing charge with the N substrate, acting as dielectrics to reduce the E-field above the pillars.
-
公开(公告)号：US10677664B1
公开(公告)日：2020-06-09
申请号：US16416390
申请日：2019-05-20
发明人： Chun Fai Wong , Tai Yin Wong , Guangjie Cai
IPC分类号： G01K15/00
摘要： A single-temperature-point temperature-sensitivity sensor assumes that all sensitivity lines converge at absolute zero temperature, so during calibration measurement is needed at only one temperature. A sensor output voltage is generated by current from a mirrored current source flowing through a variable resistor. During calibration, the resistance of the variable resistor and the mirror ratio of the mirrored current source are adjusted. An error amplifier compares voltages generated by unit currents generated by unit current sources to adjust the unit current sources and the mirrored current source. Each unit current flows through a grounded-base PNP transistor. A switchable PNP transistor is in parallel with one of the grounded-base PNP transistors and has its base switched on and off to adjust the PNP current for two measurements. The difference between the two measurements is compared to a calibration target to adjust the variable resistor and mirror ratio during calibration at a single temperature.
-
公开(公告)号：US10418978B1
公开(公告)日：2019-09-17
申请号：US16253446
申请日：2019-01-22
发明人： Chung Fai Au Yeung , Gordon Chung , Hok San Yu
IPC分类号： H03K3/017
摘要： An integrator in a duty-cycle adjustment circuit has an adjustable charging current provided by a switched current-source array in response to configuration signals from the calibration logic. The integrator's ramp voltage is compared to a threshold voltage by a comparator to generate an output clock. A tunable voltage reference generates a reference voltage that can be tuned by configuration signals from the calibration logic. The reference voltage is divided by a tunable voltage divider, which selects different fractions of the reference voltage for use as the threshold voltage. During calibration, calibration logic repeatedly raises the reference voltage or reduces the charging current from the switched current-source array until a peak voltage of the ramp voltage equals the reference voltage, when a zero duty onset detector detects that the output clock has stopped pulsing. The configuration signals at the zero duty onset condition are stored and used for normal operation.
-
公开(公告)号：US10305425B2
公开(公告)日：2019-05-28
申请号：US15796961
申请日：2017-10-30
发明人： Huimin Guo , Zhongliang Zhou , Yat Tung Lai
IPC分类号： H03B5/24 , H03K3/0231 , H03B5/04
摘要： An RC oscillator has a variable capacitor that sets the output frequency. The variable capacitor has m binary-weighted switched capacitor arrays, and each binary-weighted switched capacitor array has binary-weighted capacitors. p binary bits are decoded into an m-bit thermometer code that selects one of the m binary-weighted switched capacitor arrays to use n binary bits to switch its binary-weighted capacitors. Other binary-weighted switched capacitor arrays have all their capacitors switched on, or all their capacitors switched off by the thermometer code. The smallest or unit capacitance of each binary-weighted switched capacitor array is adjusted to compensate for the non-linear reciprocal relationship of frequency being proportional to 1/RC. The unit capacitance is increased for each successive binary-weighted switched capacitor array to reset to the ideal linear relationship of the (p,n)-bit code to frequency.
-
-
-
-
-
-
-
-
-
搜索结果
375 条记录 (耗时 0.036 秒)