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1.发明授权公开(公告)号：US10777689B1
公开(公告)日：2020-09-15
申请号：US16657376
申请日：2019-10-18
发明人： Shu Kin Yau , Siu Wai Wong
摘要： A shielded Schottky heterojunction power transistor is made from a Silicon-Carbide (SiC) wafer with SiC epitaxial layers including a N+ source and a Silicon N-epitaxial layer under the gate with higher channel mobility than SiC. The bulk of the wafer is a N+ SiC drain contacted by backside metal. A trench is formed between heterojunction transistors. Metal contacting the N+ source is extended into the trench to form a Schottky diode with the N-SiC substrate. P+ taps on the sides of the trench connect the metal to a P-SiC body diode under the heterojunction gate, and also prevent the Schottky metal from directly contacting the P body diode. Buried P pillars with P+ pillar caps are formed under the trench Schottky diode and under the heterojunction transistors. The P pillars provide shielding by balancing charge with the N substrate, acting as dielectrics to reduce the E-field above the pillars.
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公开(公告)号：US10100420B2
公开(公告)日：2018-10-16
申请号：US14983508
申请日：2015-12-29
发明人： Yaofeng Sun , Minjie Xu , Shun Yee Lao , Shu Kin Yau
IPC分类号： C25D3/38
摘要： The presently claimed invention provides a plating additive for electrodeposition, and the corresponding fabrication method thereof. The plating additive of the present invention enables to electroplate holes on a substrate with good height uniformity within a feature and among features at different diameters.
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公开(公告)号：US09991161B1
公开(公告)日：2018-06-05
申请号：US15451566
申请日：2017-03-07
发明人： Yaofeng Sun , Sha Xu , Shu Kin Yau
IPC分类号： H01L21/44 , H01L21/768 , H01L21/288 , H01L21/3205 , H01L21/3213
CPC分类号： H01L21/76898 , H01L21/288 , H01L21/2885 , H01L21/32051 , H01L21/76879
摘要： A method for filling a through hole (TH) located on a substrate is provided. The TH is a continuous channel having an upper rim, a lower rim and an interior surface. In one embodiment, the method comprises steps (a)-(d). In the step (a), a conductive material (CM) is deposited over the substrate to thereby deposit a layer of the CM around the rims and on the interior surface. In the step (b), the deposited CM is etched. In particular, the etching step selectively removes more CM deposited at the rims relative to CM deposited at a mid-section of the interior surface of the channel. In the step (c), the steps (a) and (b) are optionally repeated until the channel is sealed at the mid-section by a bridge formed of CM. In the step (d), the CM is further deposited over the substrate to thereby completely fill the TH.
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公开(公告)号：US09617653B2
公开(公告)日：2017-04-11
申请号：US14105154
申请日：2013-12-12
发明人： Yaofeng Sun , Minghui Gao , Shu Kin Yau , Min Gao
IPC分类号： C25D17/12 , C25D21/12 , G01N27/403 , C25D5/18
CPC分类号： C25D21/12 , C25D5/18 , C25D17/12 , G01N27/403
摘要： The presently claimed invention provides an electrochemical analytical apparatus and a method for evaluating performance of electroplating formulations of electrolyte solutions used for via filling. The electrochemical analytical apparatus comprises an electric power generating device, an electrical output signal measurement device, an electrochemical measurement device, and a motion generator. The electrochemical measurement device of the present invention comprises a supporting structure, a cavity, a cavity electrode, and a surface electrode. The electrical output signals of the cavity electrode and the surface electrode are measured during electroplating for calculating a filling performance value. The presently claimed invention provides an accurate, fast and cost effective method for evaluating performance of electroplating formulations, following with choosing the electroplating formulation of the highest FP value for actual microvia filling process.
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