公开(公告)号：US1558900A

公开(公告)日：1925-10-27

申请号：US70939824

申请日：1924-04-28

Applicant: UNION SWITCH & SIGNAL CO

Inventor： LEWIS LLOYD V

IPC: B61L3/22

CPC classification number: B61L3/221

公开(公告)号：US07535039B1

公开(公告)日：2009-05-19

申请号：US11453819

申请日：2006-06-16

Applicant: Eric J. Stewart ,  Stephen Van Campen ,  Rowland C. Clarke

Inventor： Eric J. Stewart ,  Stephen Van Campen ,  Rowland C. Clarke

IPC: H01L29/80

CPC classification number: H01L29/7722 ,  H01L29/66416

Abstract: A dual gate power switch comprised of a vertical arrangement of a normally off SIT (static induction transistor) in series with a normally on SIT in a monolithic semiconductor structure. The structure includes a first pillar having at the base thereof laterally extending shoulder portions having sections of a first gate for controlling the normally off SIT. The structure includes a second pillar, of a width greater than the first pillar and which also has laterally extending shoulder portions having sections of a second gate for controlling the normally on SIT. Contacts are provided for SIT operation.

Abstract translation: 一种双栅极功率开关，其包括与单片半导体结构中的常规SIT串联的常闭SIT（静态感应晶体管）的垂直布置。 该结构包括：第一柱，其底部具有横向延伸的肩部，其具有用于控制常关的SIT的第一门的部分。 该结构包括宽度大于第一柱的第二柱，并且还具有横向延伸的肩部，其具有用于控制正常在SIT上的第二浇口的部分。 提供联系人用于SIT操作。

公开(公告)号：US07474635B2

公开(公告)日：2009-01-06

申请号：US10702023

申请日：2003-11-05

Applicant: Stuart T. Linsky ,  Harvey L Berger

Inventor： Stuart T. Linsky ,  Harvey L Berger

IPC: H04J4/00 ,  H04B7/14

CPC classification number: H04B7/2043 ,  Y02D70/446

Abstract: A technique for reducing power requirements in a communication transponder by converting signals in multiple uplink channels carried in frequency division multiplexed (FDM) form on multiple uplink beams, to a lesser number of downlink beams that operate in time division multiplexing (TDM) but at a bandwidth different from and preferably greater than the bandwidth of the uplink channels. Because the TDM downlinks can utilize amplifiers operating at or near peak power, whereas conventional FDM downlinks must operate with amplifiers backed off to minimize intermodulation products, use of the TDM downlinks effects significant power savings.

Abstract translation: 通过将在多个上行链路波束上以频分复用（FDM）形式携带的多个上行链路信道中的信号转换为在时分复用（TDM）中操作的较少数量的下行链路波束来减少通信应答器中的功率需求的技术， 带宽不同于，优选大于上行链路信道的带宽。 因为TDM下行链路可以利用在峰值功率或接近峰值功率工作的放大器，而传统的FDM下行链路必须与退出的放大器一起工作，以最小化互调产物，因此TDM下行链路的使用会实现显着的功率节省。

公开(公告)号：US07084040B2

公开(公告)日：2006-08-01

申请号：US10830729

申请日：2004-04-23

Applicant: Vincent Gambin ,  Donald J. Sawdai

Inventor： Vincent Gambin ,  Donald J. Sawdai

IPC: H01L21/331

CPC classification number: H01L21/02496 ,  H01L21/02387 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02549 ,  H01L21/02639

Abstract: Formation of a regrowth layer of a Group III–V semiconductor material is facilitated by prior formation of an intermediate layer, selected primarily for its smooth morphology properties. The intermediate layer is formed over an underlying substrate and over a dielectric layer formed over portions of the substrate. The intermediate layer maintains the monocrystalline properties of the underlying substrate in regions other than those covered by the dielectric layer, and improves the electrical and morphology properties of the regrowth layer formed over the intermediate layer.

Abstract translation: 通过预先形成主要由于其光滑形态特性选择的中间层，促进了III-V族半导体材料的再生长层的形成。 中间层形成在下面的衬底之上并且形成在衬底的部分上形成的电介质层上。 中间层保持底层基板在不同于由介电层覆盖的那些区域以外的区域的单晶性质，并改善了在中间层上形成的再生长层的电学和形貌特性。

公开(公告)号：US07038293B2

公开(公告)日：2006-05-02

申请号：US10811512

申请日：2004-03-29

Applicant: Youngmin A. Choi ,  Christine Geosling ,  Henry Abbink

Inventor： Youngmin A. Choi ,  Christine Geosling ,  Henry Abbink

IPC: H01L29/00

CPC classification number: H01L21/30655 ,  B81C1/00579

Abstract: An apparatus in one example comprises a wafer portion that comprises a conduction layer. Upon exposure of the conduction layer during a etch of the wafer portion, the conduction layer serves to dissipate a portion of a charge buildup on the wafer portion during an etch of the wafer portion.

Abstract translation: 一个示例中的装置包括包括导电层的晶片部分。 在晶片部分的蚀刻期间，当导电层暴露时，导电层用于在晶片部分的蚀刻期间耗散晶片部分上的电荷积累的一部分。

公开(公告)号：US07038256B1

公开(公告)日：2006-05-02

申请号：US11003575

申请日：2004-12-03

Applicant: Donald J. Sawdai ,  Augusto L. Gutierrez-Aitken ,  Tsung-Pei Chin

Inventor： Donald J. Sawdai ,  Augusto L. Gutierrez-Aitken ,  Tsung-Pei Chin

IPC: H01L31/0328

CPC classification number: H01L29/7371 ,  H01L29/0817 ,  H01L29/1004

Abstract: A double heterojunction bipolar transistor structure having desirable properties of a low base-emitter turn-on voltage and no electron blocking discontinuities in the base-collector junction. These properties are achieved by selecting base, emitter and collector materials to provide a bandgap profile that exhibits abrupt transitions at the heterojunctions, such that both abrupt transitions are due to transitions in the valence band edge of the bandgap, but not in the conductive band edge of the bandgap.

Abstract translation: 具有低基极 - 发射极导通电压和基极 - 集电极结中电子阻挡不连续性的所需特性的双异质结双极晶体管结构。 这些性质通过选择基极，发射极和集电极材料来实现，以提供在异质结处表现出突变的带隙分布，使得两个突变都是由于带隙的价带边缘中的跃迁，而不是导电带边缘 的带隙。

公开(公告)号：US20050280628A1

公开(公告)日：2005-12-22

申请号：US11126255

申请日：2005-05-11

Applicant: Charles Adams ,  Harvey Nathanson ,  Robert Howell ,  Garrett Storaska ,  William Hall

Inventor： Charles Adams ,  Harvey Nathanson ,  Robert Howell ,  Garrett Storaska ,  William Hall

IPC: G09G5/00 ,  H04N5/74 ,  H04N17/00

CPC classification number: H04N9/3185 ,  H04N5/74 ,  H04N9/3194

Abstract: A high resolution pen-sized projector for controlling the position and size of an image generated by a closed loop control system consists of four major system components including: a virtual VGA display located inside of a XGA display, a position acquisition system, a displacement compensating control system to determine correct position of the VGA display inside of the XGA display, and a dark display area of the background portion of the XGA display.

Abstract translation: 用于控制由闭环控制系统产生的图像的位置和大小的高分辨率笔式投影仪由四个主要系统组成，包括：位于XGA显示器内部的虚拟VGA显示器，位置获取系统，位移补偿 控制系统确定XGA显示器内部的VGA显示器的正确位置，以及XGA显示器背景部分的暗显示区域。

公开(公告)号：US5548839A

公开(公告)日：1996-08-20

申请号：US322513

申请日：1994-10-14

Applicant: Stephen P. Caldwell ,  Marvine Harris Jr. ,  Demetrios J. Matsakis ,  Ronald W. Minarik ,  Kenneth M. Schmidt ,  Benjamin F. Weigand ,  Robert S. Prill ,  Arnold B. Siegel

Inventor： Stephen P. Caldwell ,  Marvine Harris Jr. ,  Demetrios J. Matsakis ,  Ronald W. Minarik ,  Kenneth M. Schmidt ,  Benjamin F. Weigand ,  Robert S. Prill ,  Arnold B. Siegel

IPC: H03D7/16 ,  H03J5/24 ,  H04B1/26

CPC classification number: H03J5/242 ,  H03D7/161

Abstract: A wideband RF-to-IF frequency converter providing multiple use of frequency conversion components for many different types of RF input signals. In specific examples, many different types of signals for communication, navigation, and for interrogation are processed through at least partly common frequency-conversion channels. Such RF input signals in the range from approximately 2 MHz to 2,000 MHz are converted to output IF frequencies, such as 1 MHz and 30 MHz, for further processing in the common receiver. Some narrow band signals, after conversion to IF, are subjected to off-center filtering in relatively broadband IF filters. Input RF filters are not used. Among several frequency conversion stages, only one of the local oscillator signals is tunable; but it is made tunable in relatively small, precise steps by using a double phase-locked loop arrangement in the frequency synthesizer.

Abstract translation: 宽带RF至IF频率转换器为多种不同类型的RF输入信号提供多种频率转换组件。 在具体示例中，用于通信，导航和询问的许多不同类型的信号通过至少部分共同的频率转换信道来处理。 在大约2MHz到2,000MHz的范围内的这样的RF输入信号被转换成诸如1MHz和30MHz的输出IF频率，用于在公共接收机中的进一步处理。 转换成IF后的一些窄带信号在相对较宽的IF滤波器中进行偏心滤波。 不使用输入RF滤波器。 在多个频率转换阶段中，只有一个本地振荡器信号是可调谐的; 但是通过使用频率合成器中的双锁相环布置，可以在相对较小，精确的步骤中进行可调谐。

公开(公告)号：US3006760A

公开(公告)日：1961-10-31

申请号：US76909058

申请日：1958-10-23

Applicant: GEN ANILINE & FILM CORP

Inventor： FRITZ DERSCH ,  DE ANGELUS MILLET R

IPC: G03C1/043

CPC classification number: G03C1/043

公开(公告)号：US07547586B2

公开(公告)日：2009-06-16

申请号：US11445215

申请日：2006-06-02

Applicant: Li-Shu Chen

Inventor： Li-Shu Chen

IPC: H01L21/332

CPC classification number: H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7722

Abstract: A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protect the area underneath it, and an etch removes the oxide, the third layer and a small amount of the second layer, leaving a plurality of pillars. An oxidation step grows an oxide skirt around the base of each pillar and consumes the edge portions of the third layer under the oxide to form a source. An ion implantation forms gate regions between the skirts. At the same time, a plurality of guard rings is formed. Removal of all oxide results in a semiconductor structure to which source, gate and drain connections may be made to form a static induction transistor. A greater separation between a source and gate is obtained by placing a spacer layer on the sidewalls of the pillars, either before or after formation of the skirt.

Abstract translation: 制造用于静态感应晶体管的半导体结构的方法。 三层SiC材料在基材上，顶层被厚氧化物覆盖。 具有多个条带的掩模沉积在氧化物的顶部以保护其下面的区域，并且蚀刻去除氧化物，第三层和少量的第二层，留下多个柱。 氧化步骤在每个柱的基部周围生长氧化物裙部，并且消耗氧化物下方的第三层的边缘部分以形成源。 离子注入在裙边之间形成门区。 同时，形成多个保护环。 去除所有氧化物导致可以使源极，栅极和漏极连接形成静电感应晶体管的半导体结构。 通过在裙部的形成之前或之后将间隔层放置在柱的侧壁上来获得源极和栅极之间的更大间隔。