公开(公告)号：US20080072191A1

公开(公告)日：2008-03-20

申请号：US11521095

申请日：2006-09-14

Applicant: George H. Chang ,  Yi-Kan Cheng ,  Chen-Teng Fan ,  Chen-Lin Yang ,  Yung-Chin Hou ,  Chu-Ping James Wang

Inventor： George H. Chang ,  Yi-Kan Cheng ,  Chen-Teng Fan ,  Chen-Lin Yang ,  Yung-Chin Hou ,  Chu-Ping James Wang

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5081

Abstract: This invention discloses a method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method comprising automatically reading one or more netlists, identifying one or more sub-circuits in the netlists isomorphic to at least one of predefined sub-circuits, identifying one or more device parameters for sanity checking the identified sub-circuits, and comparing the identified device parameters against the predefined checking criteria.

Abstract translation: 本发明公开了一种基于具有至少一个预定义的检查标准的一个或多个预定义子电路的完整性检查集成电路（IC）设计的方法，所述方法包括自动读取一个或多个网表，识别所述子电路中的一个或多个子电路 网表与至少一个预定义的子电路同构，识别一个或多个设备参数，以便确认所识别的子电路，以及将所识别的设备参数与预定义的检查标准进行比较。

公开(公告)号：US09093126B2

公开(公告)日：2015-07-28

申请号：US13563571

申请日：2012-07-31

Applicant: Chen-Lin Yang ,  Kao-Cheng Lin ,  Chung-Hsien Hua

Inventor： Chen-Lin Yang ,  Kao-Cheng Lin ,  Chung-Hsien Hua

IPC: G11C7/06 ,  G11C7/04 ,  G11C11/413 ,  G11C7/14

CPC classification number: G11C7/04 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C11/413

Abstract: A memory circuit is provided. The memory circuit includes a memory array having a bit line (BL), and a memory cell coupled to the BL; a sense amplifier (SA) coupled to the BL; a tracking bit line (TRKBL); and a comparator coupled to the TRKBL and configured to receive a reference voltage, and to output a strobe signal to the SA.

Abstract translation: 提供存储器电路。 存储器电路包括具有位线（BL）的存储器阵列和耦合到BL的存储器单元; 耦合到所述BL的读出放大器（SA）; 跟踪位线（TRKBL）; 以及耦合到TRKBL并被配置为接收参考电压并且将选通信号输出到SA的比较器。

公开(公告)号：US08441885B2

公开(公告)日：2013-05-14

申请号：US13051681

申请日：2011-03-18

Applicant: Wei Min Chan ,  Li-Wen Wang ,  Jihi-Yu Lin ,  Chen-Lin Yang ,  Shao-Yu Chou

Inventor： Wei Min Chan ,  Li-Wen Wang ,  Jihi-Yu Lin ,  Chen-Lin Yang ,  Shao-Yu Chou

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C8/18 ,  G11C11/413

Abstract: A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.

Abstract translation: 公开了一种字线驱动电路及相应的方法。 一种装置，包括被耦合以接收地址输入并具有解码器输出的解码器电路; 以及字线时钟选通电路，其耦合到所述解码器输出和字线时钟信号，被配置为响应于所述字线时钟信号上的边沿选择性地输出字线信号; 其中所述地址输入具有相对于所述字线时钟信号的边缘的建立时间要求，并且所述地址输入相对于所述字线时钟信号的边缘具有零或更小的保持时间要求。 公开了从字线驱动器提供字线信号的方法。

公开(公告)号：US20120236675A1

公开(公告)日：2012-09-20

申请号：US13051681

申请日：2011-03-18

Applicant: Wei Min Chan ,  Li-Wen Wang ,  Jihi-Yu Lin ,  Chen-Lin Yang ,  Shao-Yu Chou

Inventor： Wei Min Chan ,  Li-Wen Wang ,  Jihi-Yu Lin ,  Chen-Lin Yang ,  Shao-Yu Chou

IPC: G11C8/10

CPC classification number: G11C8/08 ,  G11C8/18 ,  G11C11/413

Abstract: A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.

Abstract translation: 公开了一种字线驱动电路及相应的方法。 一种装置，包括被耦合以接收地址输入并具有解码器输出的解码器电路; 以及字线时钟选通电路，其耦合到所述解码器输出和字线时钟信号，被配置为响应于所述字线时钟信号上的边沿选择性地输出字线信号; 其中所述地址输入具有相对于所述字线时钟信号的边缘的建立时间要求，并且所述地址输入相对于所述字线时钟信号的边缘具有零或更小的保持时间要求。 公开了从字线驱动器提供字线信号的方法。

公开(公告)号：US20100157692A1

公开(公告)日：2010-06-24

申请号：US12338732

申请日：2008-12-18

Applicant: Li-Wen Wang ,  Yen-Huei Chen ,  Chen-Lin Yang ,  Hsien-Yu Pan ,  Shao-Yu Chou ,  Hung-Jen Liao

Inventor： Li-Wen Wang ,  Yen-Huei Chen ,  Chen-Lin Yang ,  Hsien-Yu Pan ,  Shao-Yu Chou ,  Hung-Jen Liao

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C11/413 ,  G11C5/04 ,  G11C5/147

Abstract: An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.

Abstract translation: 集成电路结构包括存储器。 存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。 第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。 第一功率块具有第一输入和第一输出。 基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。 第二功率块具有第二输入和第二输出。 第一输入和第二输入互连。 第一个输出和第二个输出相互连接。

公开(公告)号：US20140036580A1

公开(公告)日：2014-02-06

申请号：US13563571

申请日：2012-07-31

Applicant: Chen-Lin YANG ,  Kao-Cheng LIN ,  Chung-Hsien HUA

Inventor： Chen-Lin YANG ,  Kao-Cheng LIN ,  Chung-Hsien HUA

IPC: G11C11/00

CPC classification number: G11C7/04 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C11/413

Abstract: A memory circuit is provided. The memory circuit includes a memory array having a bit line (BL), and a memory cell coupled to the BL; a sense amplifier (SA) coupled to the BL; a tracking bit line (TRKBL); and a comparator coupled to the TRKBL and configured to receive a reference voltage, and to output a strobe signal to the SA.

Abstract translation: 提供存储器电路。 存储器电路包括具有位线（BL）的存储器阵列和耦合到BL的存储器单元; 耦合到所述BL的读出放大器（SA）; 跟踪位线（TRKBL）; 以及耦合到TRKBL并被配置为接收参考电压并且将选通信号输出到SA的比较器。

公开(公告)号：US08213241B2

公开(公告)日：2012-07-03

申请号：US12706099

申请日：2010-02-16

Applicant: Chen-Lin Yang

Inventor： Chen-Lin Yang

IPC: G11C7/00

CPC classification number: G11C7/08

Abstract: A memory includes a memory cell coupled to a data line. A sense amplifier is coupled to the data line. A power supply node has a first voltage. The first voltage is provided to the sense amplifier. A charge pump circuit is coupled to the sense amplifier. The charge pump circuit is configured to provide a second voltage to the sense amplifier when a read operation is performed.

Abstract translation: 存储器包括耦合到数据线的存储单元。 读出放大器耦合到数据线。 电源节点具有第一电压。 第一电压被提供给读出放大器。 电荷泵电路耦合到读出放大器。 电荷泵电路被配置为当执行读取操作时向读出放大器提供第二电压。

公开(公告)号：US20120110530A1

公开(公告)日：2012-05-03

申请号：US12913949

申请日：2010-10-28

Applicant: Chen-Lin YANG ,  Wei Min CHAN

Inventor： Chen-Lin YANG ,  Wei Min CHAN

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5068

Abstract: The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified according to a predetermined maximum value for at least one of an estimated voltage drop along a signal path in the layout or an estimated current density on the signal path. If the at least one layout rule is violated, a violation is indicated.

Abstract translation: 本申请公开了根据电路设计制备用于制造集成电路芯片的布局的方法。 在至少一个实施例中，生成用于基于电路设计的布局的图案。 在生成图案之后，确定在布局中是否违反了至少一个布局规则，根据预定的最大值来指定至少一个布局规则，用于沿着信号路径的估计电压降中的至少一个 信号路径上的布局或估计的电流密度。 如果违反了至少一个布局规则，则会显示违规。

公开(公告)号：US08077517B2

公开(公告)日：2011-12-13

申请号：US12338732

申请日：2008-12-18

Applicant: Li-Wen Wang ,  Yen-Huei Chen ,  Chen-Lin Yang ,  Hsien-Yu Pan ,  Shao-Yu Chou ,  Hung-Jen Liao

Inventor： Li-Wen Wang ,  Yen-Huei Chen ,  Chen-Lin Yang ,  Hsien-Yu Pan ,  Shao-Yu Chou ,  Hung-Jen Liao

IPC: G11C11/34

CPC classification number: G11C11/413 ,  G11C5/04 ,  G11C5/147

Abstract: An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.

Abstract translation: 集成电路结构包括存储器。 存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。 第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。 第一功率块具有第一输入和第一输出。 基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。 第二功率块具有第二输入和第二输出。 第一输入和第二输入互连。 第一个输出和第二个输出相互连接。

公开(公告)号：US08990751B2

公开(公告)日：2015-03-24

申请号：US12913949

申请日：2010-10-28

Applicant: Chen-Lin Yang ,  Wei Min Chan

Inventor： Chen-Lin Yang ,  Wei Min Chan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5068

Abstract: The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified according to a predetermined maximum value for at least one of an estimated voltage drop along a signal path in the layout or an estimated current density on the signal path. If the at least one layout rule is violated, a violation is indicated.

Abstract translation: 本申请公开了根据电路设计制备用于制造集成电路芯片的布局的方法。 在至少一个实施例中，生成用于基于电路设计的布局的图案。 在生成图案之后，确定在布局中是否违反了至少一个布局规则，根据预定的最大值来指定至少一个布局规则，用于沿着信号路径的估计电压降中的至少一个 信号路径上的布局或估计的电流密度。 如果违反了至少一个布局规则，则会显示违规。