公开(公告)号：US08767494B2

公开(公告)日：2014-07-01

申请号：US13493118

申请日：2012-06-11

Applicant: Chen-Lin Yang ,  Chung-Yi Wu ,  Yu-Hao Hsu

Inventor： Chen-Lin Yang ,  Chung-Yi Wu ,  Yu-Hao Hsu

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C7/12 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.

Abstract translation: 公开了一种字线追踪电路及相应的方法，包括具有与之相关联的阻抗特征的跟踪字线，其对存储器件中的一行存储单元进行建模，其中跟踪字线具有接近具有近似的字线脉冲信号的近端 结束上升脉冲沿和近端下降脉冲沿。 跟踪字线也有一个远端。 跟踪单元组件耦合到接收字线脉冲信号的跟踪字线的远端。 最后，电路包括耦合到跟踪单元的跟踪位线预充电电路，其被配置为使用近端字线脉冲信号对与跟踪单元相关联的跟踪位线进行预充电。

公开(公告)号：US20130094308A1

公开(公告)日：2013-04-18

申请号：US13273369

申请日：2011-10-14

Applicant: Chen-Lin Yang ,  Wei Min Chan ,  Chung-Hsien Hua

Inventor： Chen-Lin Yang ,  Wei Min Chan ,  Chung-Hsien Hua

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C7/22 ,  G11C11/418

Abstract: A semiconductor memory includes a word line driver and a negative voltage generator. The word line driver includes a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source. The negative voltage generator is configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line.

Abstract translation: 半导体存储器包括字线驱动器和负电压发生器。 字线驱动器包括第一反相器，被配置为以由第一电压源提供的第一电压和由第二电压源提供的第二电压中的一个驱动字线。 负电压发生器被配置为响应于用于执行耦合到第一反相器的存储器位单元的读取或写入操作中的至少一个的控制信号，将相对于第二电压的负电压提供给第一反相器的输入 字线。

公开(公告)号：US07467365B2

公开(公告)日：2008-12-16

申请号：US11521095

申请日：2006-09-14

Applicant: George H. Chang ,  Yi-Kan Cheng ,  Chen-Teng Fan ,  Chen-Lin Yang ,  Yung-Chin Hou ,  Chu-Ping James Wang

Inventor： George H. Chang ,  Yi-Kan Cheng ,  Chen-Teng Fan ,  Chen-Lin Yang ,  Yung-Chin Hou ,  Chu-Ping James Wang

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: This invention discloses a method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method comprising automatically reading one or more netlists, identifying one or more sub-circuits in the netlists isomorphic to at least one of predefined sub-circuits, identifying one or more device parameters for sanity checking the identified sub-circuits, and comparing the identified device parameters against the predefined checking criteria.

公开(公告)号：US08830784B2

公开(公告)日：2014-09-09

申请号：US13273369

申请日：2011-10-14

Applicant: Chen-Lin Yang ,  Wei Min Chan ,  Chung-Hsien Hua

Inventor： Chen-Lin Yang ,  Wei Min Chan ,  Chung-Hsien Hua

IPC: G11C8/00 ,  G11C8/08 ,  G11C7/22 ,  G11C11/418

CPC classification number: G11C8/08 ,  G11C7/22 ,  G11C11/418

Abstract: A semiconductor memory includes a word line driver and a negative voltage generator. The word line driver includes a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source. The negative voltage generator is configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line.

Abstract translation: 半导体存储器包括字线驱动器和负电压发生器。 字线驱动器包括第一反相器，被配置为以由第一电压源提供的第一电压和由第二电压源提供的第二电压中的一个驱动字线。 负电压发生器被配置为响应于用于执行耦合到第一反相器的存储器位单元的读取或写入操作中的至少一个的控制信号，将相对于第二电压的负电压提供给第一反相器的输入 字线。

公开(公告)号：US20130329505A1

公开(公告)日：2013-12-12

申请号：US13493118

申请日：2012-06-11

Applicant: Chen-Lin Yang ,  Chung-Yi Wu ,  Yu-Hao Hsu

Inventor： Chen-Lin Yang ,  Chung-Yi Wu ,  Yu-Hao Hsu

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.

Abstract translation: 公开了一种字线跟踪电路和相应的方法，并且包括具有与之相关联的阻抗特性的跟踪字线，其对存储器件中的一行存储器单元进行建模，其中跟踪字线行具有近端，其接收具有 近端上升脉冲沿和近端下降脉冲沿。 跟踪字线也有一个远端。 跟踪单元组件耦合到接收字线脉冲信号的跟踪字线的远端。 最后，电路包括耦合到跟踪单元的跟踪位线预充电电路，其被配置为使用近端字线脉冲信号对与跟踪单元相关联的跟踪位线进行预充电。

公开(公告)号：US08391097B2

公开(公告)日：2013-03-05

申请号：US12786791

申请日：2010-05-25

Applicant: Wei Min Chan ,  Yen-Huei Chen ,  Chen-Lin Yang ,  Hsiu-Hui Yang ,  Shao-Yu Chou

Inventor： Wei Min Chan ,  Yen-Huei Chen ,  Chen-Lin Yang ,  Hsiu-Hui Yang ,  Shao-Yu Chou

IPC: G11C11/34 ,  G11C7/00

CPC classification number: G11C16/30 ,  G11C8/08

Abstract: A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.

Abstract translation: 用于驱动存储器阵列中的字线的字线驱动电路包括具有一对地址输入和输出的NAND电路，具有反相器电源节点的输出反相器电路，耦合到NAND的输出的输入 电路和用于提供字线信号的输出，耦合在第一电源节点和逆变器电源节点之间的电源栅极以及耦合到电源门的控制电路。 控制电路控制电源门以响应于NAND电路的输出将字线驱动电路置于有效或待机模式。

公开(公告)号：US08296705B2

公开(公告)日：2012-10-23

申请号：US12683599

申请日：2010-01-07

Applicant: Chen-Lin Yang

Inventor： Chen-Lin Yang

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  H01L27/112 ,  H01L27/11226

Abstract: A method includes receiving instructions for designing a ROM array, generating netlists for the ROM array, generating a data file representing a physical layout of the ROM array on a semiconductor wafer, and storing the data file in a computer readable storage medium. The instructions for the ROM array define a layout for a first unit including a first bit cell coupled to a first word line, a bus that may be coupled and uncoupled to a first power supply having a first voltage level, a layout for a second unit coupled to a second word line, and a layout for a third unit having an isolation device and being configured to share a bit line contact with the second unit or another third unit. The layout for the second unit is configured to be arranged at an edge of the ROM array and includes a dummy device.

Abstract translation: 一种方法包括接收用于设计ROM阵列的指令，为ROM阵列生成网表，生成表示半导体晶片上的ROM阵列的物理布局的数据文件，以及将数据文件存储在计算机可读存储介质中。 ROM阵列的指令定义了第一单元的布局，该第一单元包括耦合到第一字线的第一位单元，可以耦合并分离到具有第一电压电平的第一电源的总线，用于第二单元的布局 耦合到第二字线，以及具有隔离装置的第三单元的布局，并且被配置为与第二单元或另一第三单元共享位线接触。 第二单元的布局被配置为布置在ROM阵列的边缘并且包括虚设装置。

公开(公告)号：US20110292754A1

公开(公告)日：2011-12-01

申请号：US12786791

申请日：2010-05-25

Applicant: Wei Min Chan ,  Yen-Huei Chen ,  Chen-Lin Yang ,  Hsiu-Hui Yang ,  Shao-Yu Chou

Inventor： Wei Min Chan ,  Yen-Huei Chen ,  Chen-Lin Yang ,  Hsiu-Hui Yang ,  Shao-Yu Chou

IPC: G11C8/08

CPC classification number: G11C16/30 ,  G11C8/08

Abstract: A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.

Abstract translation: 用于驱动存储器阵列中的字线的字线驱动电路包括具有一对地址输入和输出的NAND电路，具有反相器电源节点的输出反相器电路，耦合到NAND的输出的输入 电路和用于提供字线信号的输出，耦合在第一电源节点和逆变器电源节点之间的电源栅极以及耦合到电源门的控制电路。 控制电路控制电源门以响应于NAND电路的输出将字线驱动电路置于有效或待机模式。

公开(公告)号：US20110199850A1

公开(公告)日：2011-08-18

申请号：US12706099

申请日：2010-02-16

Applicant: Chen-Lin YANG

Inventor： Chen-Lin YANG

IPC: G11C5/14

CPC classification number: G11C7/08

Abstract: A memory includes a memory cell coupled to a data line. A sense amplifier is coupled to the data line. A power supply node has a first voltage. The first voltage is provided to the sense amplifier. A charge pump circuit is coupled to the sense amplifier. The charge pump circuit is configured to provide a second voltage to the sense amplifier when a read operation is performed.

Abstract translation: 存储器包括耦合到数据线的存储单元。 读出放大器耦合到数据线。 电源节点具有第一电压。 第一电压被提供给读出放大器。 电荷泵电路耦合到读出放大器。 电荷泵电路被配置为当执行读取操作时向读出放大器提供第二电压。

公开(公告)号：US20110055783A1

公开(公告)日：2011-03-03

申请号：US12683599

申请日：2010-01-07

Applicant: Chen-Lin YANG

Inventor： Chen-Lin YANG

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  H01L27/112 ,  H01L27/11226

Abstract: A method includes receiving instructions for designing a ROM array, generating netlists for the ROM array, generating a data file representing a physical layout of the ROM array on a semiconductor wafer, and storing the data file in a computer readable storage medium. The instructions for the ROM array define a layout for a first unit including a first bit cell coupled to a first word line, a bus that may be coupled and uncoupled to a first power supply having a first voltage level, a layout for a second unit coupled to a second word line, and a layout for a third unit having an isolation device and being configured to share a bit line contact with the second unit or another third unit. The layout for the second unit is configured to be arranged at an edge of the ROM array and includes a dummy device.

Abstract translation: 一种方法包括接收用于设计ROM阵列的指令，为ROM阵列生成网表，生成表示半导体晶片上的ROM阵列的物理布局的数据文件，以及将数据文件存储在计算机可读存储介质中。 ROM阵列的指令定义了第一单元的布局，该第一单元包括耦合到第一字线的第一位单元，可以耦合并分离到具有第一电压电平的第一电源的总线，用于第二单元的布局 耦合到第二字线，以及具有隔离装置的第三单元的布局，并且被配置为与第二单元或另一第三单元共享位线接触。 第二单元的布局被配置为布置在ROM阵列的边缘并且包括虚设装置。