公开(公告)号：US07253662B2

公开(公告)日：2007-08-07

申请号：US10907957

申请日：2005-04-22

Applicant: Yu-Wen Tsai ,  Cheng-I Huang

Inventor： Yu-Wen Tsai ,  Cheng-I Huang

IPC: H03K19/00

CPC classification number: H01L27/0207 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an electric device having power switches around a logic circuit including: forming a logic circuit on a substrate; forming a plurality of power switches around the logic circuit; and coupling first ends of the power switches to a voltage end, and coupling second ends of the power switches to a power receiver of the logic circuit.

Abstract translation: 一种用于形成具有围绕逻辑电路的电源开关的电气装置的方法，包括：在基板上形成逻辑电路; 在逻辑电路周围形成多个电源开关; 并且将所述功率开关的第一端耦合到电压端，以及将所述功率开关的第二端耦合到所述逻辑电路的功率接收器。

公开(公告)号：US07165232B2

公开(公告)日：2007-01-16

申请号：US10733095

申请日：2003-12-11

Applicant: Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang ,  Ya-Yun Liu

Inventor： Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang ,  Ya-Yun Liu

IPC: G06F17/50 ,  H01L29/40

CPC classification number: H01L27/11898 ,  H01L27/0207

Abstract: An I/O circuit placement method. In the I/O circuit placement method, at least two rows of I/O circuits are placed on a first side of the chip, and each I/O circuit has a head section and a tail section. The placement direction of the head section and the tail section is perpendicular to the placement direction of the I/O circuits in the rows. The semiconductor further has a core circuit disposed on the chip, wherein the rows of I/O circuits are disposed outside the core circuit and are at the periphery of the chip. Due to the I/O circuit placement in the semiconductor device, the present invention reduces the area of the semiconductor chip and fabrication cost.

Abstract translation: 一种I / O电路放置方法。 在I / O电路放置方法中，至少两行I / O电路放置在芯片的第一侧上，并且每个I / O电路具有头部和尾部。 头部和尾部的放置方向垂直于行中的I / O电路的放置方向。 半导体还具有设置在芯片上的核心电路，其中I / O电路行设置在核心电路的外部并且位于芯片的外围。 由于半导体器件中的I / O电路布置，本发明减小了半导体芯片的面积和制造成本。

公开(公告)号：US06978411B2

公开(公告)日：2005-12-20

申请号：US10265700

申请日：2002-10-08

Applicant: Cheng-I Huang ,  Chen-Teng Fan ,  Wang-Jin Chen ,  Jyh-Herny Wang

Inventor： Cheng-I Huang ,  Chen-Teng Fan ,  Wang-Jin Chen ,  Jyh-Herny Wang

IPC: G11C29/56 ,  G01R31/28

CPC classification number: G11C29/56012 ,  G11C29/56

Abstract: A memory test system for peak power reduction. The memory test system includes a plurality of memories, a plurality of memory built-in self-test circuits and a plurality of delay units. Each of the memory built-in self-test circuits comprises a built-in self-test controller for receiving a clock signal and producing a plurality of required control signals to test one of the memories. Each of the delay units is coupled between two adjacent built-in self-test controllers. The clock signal input to one of the built-in self-test controllers is received by the delay unit to produce a delayed clock signal, and the delay unit outputs the delayed clock signal to the other.

Abstract translation: 用于峰值功率降低的记忆测试系统。 存储器测试系统包括多个存储器，多个存储器内置自检电路和多个延迟单元。 每个存储器内置的自检电路包括内置的自检控制器，用于接收时钟信号并产生多个所需的控制信号以测试其中一个存储器。 每个延迟单元耦合在两个相邻的内置自检控制器之间。 输入到内置自检控制器之一的时钟信号由延迟单元接收以产生延迟的时钟信号，并且延迟单元将延迟的时钟信号输出到另一个。

公开(公告)号：US20140019930A1

公开(公告)日：2014-01-16

申请号：US13547251

申请日：2012-07-12

Applicant: Ping-Hung YUH ,  Cheng-I HUANG ,  Chung-Hsing WANG

Inventor： Ping-Hung YUH ,  Cheng-I HUANG ,  Chung-Hsing WANG

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5081

Abstract: In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout.

Abstract translation: 在由至少一个处理器执行的半导体器件设计方法中，提取在半导体器件的布局的区域内的电气元件之间的至少一个第一寄生参数和在布局区域之外的电气元件之间的至少一个第二寄生参数 通过不同的工具。 提取的寄生参数被并入到布局中。

公开(公告)号：US20110316122A1

公开(公告)日：2011-12-29

申请号：US13225756

申请日：2011-09-06

Applicant: Yu-Pin TSAI ,  Cheng-I Huang ,  Yao-Hui Hu

Inventor： Yu-Pin TSAI ,  Cheng-I Huang ,  Yao-Hui Hu

IPC: H01L21/268 ,  H01L29/06

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2223/54433 ,  H01L2224/16 ,  H01L2924/01025 ,  H01L2924/01084 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/00

Abstract: A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon.

Abstract translation: 提供了晶片激光打标方法。 首先，提供具有彼此相对的第一表面（活性表面）和第二表面（背面）的晶片。 接下来，晶片变薄。 然后，将薄的晶片固定在非UV带上，使得晶片的第二表面附接到带上。 最后，执行激光标记步骤，使得激光穿透非UV带并且在晶片的第二表面上标记图案。 根据本实施例的激光标记方法，图案由残留在晶片的第二表面上的非UV残余物形成，并且胶合残余物的成分至少包括硅和碳的元素。