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    Method of thinning a wafer
    2.
    发明申请
    Method of thinning a wafer 审中-公开
    薄晶片的方法

    公开(公告)号：US20080200037A1

    公开(公告)日：2008-08-21

    申请号：US11953846

    申请日：2007-12-10

    Applicant: Yu-Pin Tsai ,  Cheng-I Huang

    Inventor： Yu-Pin Tsai ,  Cheng-I Huang

    IPC: H01L21/00

    CPC classification number: H01L21/304

    Abstract: A method of thinning wafer is disclosed. A wafer has an active surface and a back surface is provided. A plurality of protruding components may be disposed on the active surface. The wafer is placed in a mold and a polymeric material is formed in the mold to cover at least the active surface of the wafer. The polymeric material is cured and the mold is removed. The back surface of the wafer is ground to thin the wafer. The polymeric material is removed to expose the active surface of the wafer and the protruding components disposed on the active surface. The polymeric material is allowed to cover the active surface of the wafer and the protruding components through the mold; accordingly, the stress produced during the grinding can be distributed uniformly on the wafer, and the wafer warpage, breakage, or collapse, or the protruding component peeling can be avoided.

    Abstract translation: 公开了一种薄化晶片的方法。 晶片具有活性表面并提供后表面。 多个突出部件可以设置在活动表面上。 将晶片放置在模具中，并且在模具中形成聚合物材料以至少覆盖晶片的活性表面。 聚合物材料固化并除去模具。 研磨晶片的背面以使晶片变薄。 去除聚合物材料以暴露晶片的活性表面和设置在活性表面上的突出组分。 允许聚合物材料通过模具覆盖晶片的活性表面和突出的部件; 因此，可以在研磨时产生的应力均匀地分布在晶片上，并且可以避免晶片的翘曲，断裂或塌陷或突出的部件剥离。

    CHIP SCALE PACKAGE AND METHOD FOR MARKING CHIP SCALE PACKAGES
    3.
    发明申请
    CHIP SCALE PACKAGE AND METHOD FOR MARKING CHIP SCALE PACKAGES 审中-公开
    芯片尺寸包装和标记芯片尺寸包装的方法

    公开(公告)号：US20080132000A1

    公开(公告)日：2008-06-05

    申请号：US11871056

    申请日：2007-10-11

    Applicant: Yu Pin TSAI ,  Kuo Pin Yang ,  Wu Chung Chiang

    Inventor： Yu Pin TSAI ,  Kuo Pin Yang ,  Wu Chung Chiang

    IPC: H01L21/00

    CPC classification number: H01L23/3114 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for marking chip scale packages at the wafer level is provided. First, a positioning step is performed to determine the position of a plurality of semi-finished chip scale packages formed on a wafer. Each of the semi-finished chip scale package includes a plurality of terminals for making external electrical connections and each die has a plurality of bonding pads on an active surface thereof. The bonding pads are electrically connected to the respective terminals wherein a backside surface of the die is exposed from a surface of the respective semi-finished chip scale package. The exposed backside surface of the die is then marked by ink-jet printing. Afterward, the ink marks on the dice are cured. Finally, the wafer is diced to obtain a plurality of separated chip scale packages.

    Abstract translation: 提供了一种用于在晶片级标记芯片级封装的方法。 首先，执行定位步骤以确定形成在晶片上的多个半成品芯片级封装的位置。 每个半成品芯片级封装包括用于进行外部电连接的多个端子，并且每个管芯在其有效表面上具有多个焊盘。 接合焊盘电连接到各个端子，其中芯片的背面从相应的半成品芯片尺寸封装的表面露出。 然后通过喷墨打印标记模具的暴露的背面。 之后，骰子上的墨迹被修复。 最后，切割晶片以获得多个分离的芯片级封装。

    Method for Manufacturing Chip Package Structures
    6.
    发明申请
    Method for Manufacturing Chip Package Structures 审中-公开
    制造芯片封装结构的方法

    公开(公告)号：US20070155049A1

    公开(公告)日：2007-07-05

    申请号：US11559036

    申请日：2006-11-13

    Applicant: Yu-Pin Tsai

    Inventor： Yu-Pin Tsai

    IPC: H01L21/00

    CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/12105 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/05099

    Abstract: A wafer-level method for manufacturing a chip package structure is disclosed. A wafer comprises a first surface and a second surface opposite thereto. The first surface has chip units disposed thereon to define scribe lines. An adhesive material is disposed between the first surface and the transparent glass for adhering the wafer to a transparent glass and leaving no gap between the first surface and the transparent glass. The wafer is vertically cut from the second surface corresponding to each scribe line of the first surface to the encapsulation adhesive material for forming scribe grooves, and then the second surface is coated with an encapsulation material for filling the scribe grooves. After removing the adhesive material and the transparent glass, the encapsulation material in each of the scribe grooves is vertically cut from the first surface, so as to form chip package structures.

    Abstract translation: 公开了用于制造芯片封装结构的晶片级方法。 晶片包括第一表面和与其相对的第二表面。 第一表面具有设置在其上的芯片单元以限定划线。 粘合材料设置在第一表面和透明玻璃之间，用于将晶片粘附到透明玻璃上，并且在第一表面和透明玻璃之间不留下间隙。 将晶片从对应于第一表面的每个划线的第二表面垂直切割到用于形成划线槽的封装粘合剂材料，然后第二表面涂覆有用于填充划线槽的封装材料。 在去除粘合剂材料和透明玻璃之后，每个划线槽中的封装材料从第一表面垂直切割，以形成芯片封装结构。

    Semiconductor wafer cassette
    7.
    发明授权
    Semiconductor wafer cassette 有权
    半导体晶片盒

    公开(公告)号：US06691876B2

    公开(公告)日：2004-02-17

    申请号：US10056357

    申请日：2002-01-25

    Applicant: Yu-Pin Tsai ,  Chih-Min Pao ,  Ching-Feng Tseng ,  Fu-Tang Chu

    Inventor： Yu-Pin Tsai ,  Chih-Min Pao ,  Ching-Feng Tseng ,  Fu-Tang Chu

    IPC: A47G1908

    CPC classification number: H01L21/6732 ,  H01L21/67326

    Abstract: A semiconductor wafer cassette has a first side wall, a second side wall opposite the first side wall, a front surface, and a back surface opposite the front surface. A body defines an internal bay portion with slots for vertically receiving wafers, each slot of the internal bay portion having one support slab. The body also includes two parallel legs for supporting the cassette and a handle for handling the cassette.

    Abstract translation: 半导体晶片盒具有第一侧壁，与第一侧壁相对的第二侧壁，前表面和与前表面相对的后表面。 主体限定具有用于垂直接收晶片的槽的内部间隔部分，内部间隔部分的每个槽具有一个支撑板。 该主体还包括用于支撑盒的两个平行腿和用于处理盒的手柄。

    WAFER LASER-MARKING METHOD AND DIE FABRICATED USING THE SAME
    8.
    发明申请
    WAFER LASER-MARKING METHOD AND DIE FABRICATED USING THE SAME 有权
    使用相同方法制作的波长激光标记方法和DIE

    公开(公告)号：US20110316122A1

    公开(公告)日：2011-12-29

    申请号：US13225756

    申请日：2011-09-06

    Applicant: Yu-Pin TSAI ,  Cheng-I Huang ,  Yao-Hui Hu

    Inventor： Yu-Pin TSAI ,  Cheng-I Huang ,  Yao-Hui Hu

    IPC: H01L21/268 ,  H01L29/06

    CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2223/54433 ,  H01L2224/16 ,  H01L2924/01025 ,  H01L2924/01084 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/00

    Abstract: A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon.

    Abstract translation: 提供了晶片激光打标方法。 首先，提供具有彼此相对的第一表面（活性表面）和第二表面（背面）的晶片。 接下来，晶片变薄。 然后，将薄的晶片固定在非UV带上，使得晶片的第二表面附接到带上。 最后，执行激光标记步骤，使得激光穿透非UV带并且在晶片的第二表面上标记图案。 根据本实施例的激光标记方法，图案由残留在晶片的第二表面上的非UV残余物形成，并且胶合残余物的成分至少包括硅和碳的元素。

    CIS Package and Method Thereof
    10.
    发明申请
    CIS Package and Method Thereof 审中-公开
    CIS封装及其方法

    公开(公告)号：US20060256222A1

    公开(公告)日：2006-11-16

    申请号：US11164891

    申请日：2005-12-09

    Applicant: Yu-Pin Tsai

    Inventor： Yu-Pin Tsai

    IPC: H04N5/335

    CPC classification number: H04N5/2253 ,  H01L27/14618 ,  H01L27/14685 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

    Abstract: A method of fabricating a CMOS image sensor (CIS) package includes: providing a transparent substrate, in which the transparent substrate includes a cavity; disposing an image sensor chip in the cavity and forming a plurality of bumps between the image sensor chip and the transparent substrate, in which the image sensor chip includes a light sensitive area; forming a barrier wall between the transparent substrate and the image sensor chip, in which the barrier wall further forms a circular pattern around the light sensitive area of the image sensor chip; and forming an underfill layer between the transparent substrate and the image sensor chip for forming a package structure.

    Abstract translation: 制造CMOS图像传感器（CIS）封装的方法包括：提供透明基板，其中所述透明基板包括空腔; 将图像传感器芯片设置在空腔中，并在图像传感器芯片和透明基板之间形成多个凸起，其中图像传感器芯片包括光敏区域; 在透明基板和图像传感器芯片之间形成阻挡壁，其中阻挡壁进一步在图像传感器芯片的感光区域周围形成圆形图案; 以及在所述透明基板和用于形成封装结构的图像传感器芯片之间形成底层填充层。

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