公开(公告)号：US08421166B2

公开(公告)日：2013-04-16

申请号：US13175443

申请日：2011-07-01

Applicant: Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang ,  Cheng-Ku Chen

Inventor： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang ,  Cheng-Ku Chen

IPC: H01L21/02 ,  H01L27/118 ,  H01L21/76

CPC classification number: H01L29/665 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y02P80/30

Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer. The opening is sealed by a sealing layer to form an air gap.

Abstract translation: 公开了一种用于形成半导体器件的方法。 提供了包括顺序地形成在其上的栅介电层和栅极电极层的基板。 在栅极电介质层和栅极电极层的侧壁上形成偏移间隔物。 在间隔物的侧壁上形成碳隔离物，然后除去碳隔离物。 使用栅极电极层和偏移间隔物作为掩模，注入衬底以形成轻掺杂区域。 该方法还可以包括提供具有顺序地形成在其上的栅极电介质层和栅极电极层的衬底。 衬底层形成在栅电极层的侧壁和衬底上。 在衬垫层的与栅电极层的侧壁相邻的部分上形成碳隔离物。 主间隔件形成在碳隔离件的侧壁上。 去除碳间隔物以在衬垫层和主间隔物之间​​形成开口。 开口由密封层密封以形成气隙。

公开(公告)号：US07291553B2

公开(公告)日：2007-11-06

申请号：US11075777

申请日：2005-03-08

Applicant: Cheng-Ku Chen ,  Min-Hwa Chi

Inventor： Cheng-Ku Chen ,  Min-Hwa Chi

IPC: H01L21/4763

CPC classification number: H01L21/76811 ,  H01L21/76808 ,  H01L21/76813

Abstract: A method for forming a dual damascene with improved profiles including providing a semiconductor process wafer including a dielectric insulating layer and an overlying hardmask layer; forming an uppermost layer of amorphous carbon substantially conformally over the hardmask layer; forming a trench line opening through at least the thickness of the amorphous carbon layer; forming a dual damascene opening comprising forming the trench line opening overlying a via opening pattern through a thickness of the hardmask layer and partially through a thickness of the dielectric insulating layer; and, filling the dual damascene opening with metal.

Abstract translation: 一种用于形成具有改进轮廓的双镶嵌的方法，包括提供包括介电绝缘层和覆盖硬掩模层的半导体工艺晶片; 基本上保形地在硬掩模层上形成无定形碳的最上层; 通过至少所述无定形碳层的厚度形成沟槽线开口; 形成双镶嵌开口，包括形成覆盖通孔开口图案的沟槽线开口，穿过硬掩模层的厚度并且部分地穿过介电绝缘层的厚度; 并用金属填充双镶嵌开口。

公开(公告)号：US20070200179A1

公开(公告)日：2007-08-30

申请号：US11360683

申请日：2006-02-24

Applicant: Cheng-Ku Chen

Inventor： Cheng-Ku Chen

IPC: H01L29/94 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/7843

Abstract: A strain enhanced CMOS device using amorphous carbon films and fabrication methods of forming the same. The amorphous carbon (a-C) film, such as fluorinated amorphous carbon (a-C:F), is formed of a tensile film or a compressive film to act a stress capping film on the pMOS device region or the nMOS device region. The amorphous carbon film also acts a contact etching stop layer during a contact hole etching process.

Abstract translation: 使用非晶碳膜的应变增强CMOS器件及其形成方法。 无定形碳（a-C）膜，如氟化无定形碳（a-C：F））由拉伸膜或压缩膜形成，以在pMOS器件区域或nMOS器件区域上起作用应力覆盖膜。 无定形碳膜还在接触孔蚀刻工艺期间起接触蚀刻停止层的作用。

公开(公告)号：US07071515B2

公开(公告)日：2006-07-04

申请号：US10619114

申请日：2003-07-14

Applicant: Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/823481 ,  H01L21/26586 ,  H01L21/76237

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract translation: 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US20060060909A1

公开(公告)日：2006-03-23

申请号：US10945762

申请日：2004-09-21

Applicant: Min-Hwa Chi ,  Wen-Chuan Chiang ,  Cheng-Ku Chen

Inventor： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Cheng-Ku Chen

IPC: H01L29/94

CPC classification number: H01L27/10805 ,  H01L27/10829 ,  H01L27/1085

Abstract: Disclosed herein is a DRAM memory cell featuring a reduced size, increased retention time, and compatibility with standard logic manufacturing processes, making it well-suited for use as embedded DRAM. The memory cell disclosed herein includes a pass-gate transistor and a storage region. The transistor includes a gate and a drain. The storage region includes a trench, which is preferably a Shallow Trench Isolation (STI). A non-insulating structure, e.g., formed of polysilicon or metal, is located in the trench as serves as a capacitor node. The trench is partially defined by a doped sidewall that serves as a source for the transistor. The poly structure and the trench sidewall are separated by a dielectric layer. The write operation involves charge transport to the non-insulating structure by direct tunneling through the dielectric layer. The read operation is assisted by Gate Induced Drain Leakage (GIDL) current generated on the surface of the sidewall.

公开(公告)号：US20050202642A1

公开(公告)日：2005-09-15

申请号：US10798178

申请日：2004-03-11

Applicant: Cheng-Ku Chen ,  Min-Hwa Chi

Inventor： Cheng-Ku Chen ,  Min-Hwa Chi

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/6659

Abstract: Methods of forming MOSFET devices featuring LDD regions offset from the edges of conductive gate structures has been developed. A first embodiment of this invention features the definition of a tapered conductive gate structure with the foot of the tapered structure larger in width than the top of the structure. Formation of an LDD region is accomplished in regions of the semiconductor substrate not covered by the tapered conductive structure. A dry etch procedure is next used to remove the foot of the tapered conductive structure resulting in an LDD region being offset from the edges of a now straight walled conductive structure. A second embodiment of this invention entails the definition of a conductive gate structure featuring notches located at the bottom of the conductive gate structure, extending inwards. Formation of an LDD region is again accomplished in regions of the semiconductor substrate not underlying the non-notched portion of the conductive gate structure, resulting in the LDD region being offset from the notched edges of the conductive gate structure.

Abstract translation: 已经开发了形成具有从导电栅极结构的边缘偏移的LDD区域的MOSFET器件的方法。 本发明的第一实施例的特征在于锥形导电栅极结构的定义，其中锥形结构的底部宽度大于结构的顶部。 在半导体衬底的未被锥形导电结构覆盖的区域中实现LDD区的形成。 接下来使用干蚀刻工艺去除锥形导电结构的脚，导致LDD区域从现在的直壁导电结构的边缘偏移。 本发明的第二实施例需要定义导电栅极结构，其特征在于位于导电栅结构底部的向内延伸的凹口。 LDD区域的形成再次在半导体衬底的不在导电栅极结构的非凹口部分下方的区域中实现，导致LDD区域偏离导电栅极结构的缺口边缘。

公开(公告)号：US20060079068A1

公开(公告)日：2006-04-13

申请号：US11288858

申请日：2005-11-29

Applicant: Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC: H01L21/76

CPC classification number: H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

公开(公告)号：US20050012173A1

公开(公告)日：2005-01-20

申请号：US10619114

申请日：2003-07-14

Applicant: Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/337 ,  H01L29/00

CPC classification number: H01L21/823481 ,  H01L21/26586 ,  H01L21/76237

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract translation: 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。