公开(公告)号：US07399679B2

公开(公告)日：2008-07-15

申请号：US11288858

申请日：2005-11-29

Applicant: Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC: H01L21/337 ,  H01L21/336 ,  H01L21/76 ,  H01L21/425

CPC classification number: H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract translation: 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US20060079068A1

公开(公告)日：2006-04-13

申请号：US11288858

申请日：2005-11-29

Applicant: Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC: H01L21/76

CPC classification number: H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

公开(公告)号：US20050012173A1

公开(公告)日：2005-01-20

申请号：US10619114

申请日：2003-07-14

Applicant: Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/337 ,  H01L29/00

CPC classification number: H01L21/823481 ,  H01L21/26586 ,  H01L21/76237

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract translation: 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US07633110B2

公开(公告)日：2009-12-15

申请号：US10945762

申请日：2004-09-21

Applicant: Min-Hwa Chi ,  Wen-Chuan Chiang ,  Cheng-Ku Chen

Inventor： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Cheng-Ku Chen

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10829 ,  H01L27/1085

Abstract: Disclosed herein is a DRAM memory cell featuring a reduced size, increased retention time, and compatibility with standard logic manufacturing processes, making it well-suited for use as embedded DRAM. The memory cell disclosed herein includes a pass-gate transistor and a storage region. The transistor includes a gate and a drain. The storage region includes a trench, which is preferably a Shallow Trench Isolation (STI). A non-insulating structure, e.g., formed of polysilicon or metal, is located in the trench as serves as a capacitor node. The trench is partially defined by a doped sidewall that serves as a source for the transistor. The poly structure and the trench sidewall are separated by a dielectric layer. The write operation involves charge transport to the non-insulating structure by direct tunneling through the dielectric layer. The read operation is assisted by Gate Induced Drain Leakage (GIDL) current generated on the surface of the sidewall.

Abstract translation: 这里公开了一种具有减小的尺寸，增加的保留时间以及与标准逻辑制造工艺的兼容性的DRAM存储单元，使其非常适合用作嵌入式DRAM。 本文公开的存储单元包括通过栅极晶体管和存储区域。 晶体管包括栅极和漏极。 存储区域包括沟槽，其优选地是浅沟槽隔离（STI）。 例如由多晶硅或金属形成的非绝缘结构位于沟槽中作为电容器节点。 沟槽部分地由用作晶体管的源极的掺杂侧壁限定。 多晶硅结构和沟槽侧壁被介电层分开。 写入操作涉及通过直接穿过介电层的隧道将电荷传输到非绝缘结构。 读取操作由在侧壁表面产生的栅极引入漏极泄漏（GIDL）电流辅助。

公开(公告)号：US07371634B2

公开(公告)日：2008-05-13

申请号：US11048485

申请日：2005-01-31

Applicant: Wen-Chuan Chiang ,  Cheng-Ku Chen ,  Mu-Chi Chiang ,  Min-Hwa Chi

Inventor： Wen-Chuan Chiang ,  Cheng-Ku Chen ,  Mu-Chi Chiang ,  Min-Hwa Chi

IPC: H01L21/8238

CPC classification number: H01L21/76829 ,  H01L21/0212 ,  H01L21/02266 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/3127 ,  H01L21/31608 ,  H01L21/31625 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823871 ,  H01L29/78 ,  H01L29/7843 ,  Y02P80/30

Abstract: A semiconductor device including a contact etch stop layer and contact hole formation method for reduced underlying material loss and improved device performance, the method including providing a semiconductor substrate including an active region including a CMOS device, STI structures, and metal silicide regions; forming a fluorine doped amorphous carbon layer over the active region; forming a PMD layer on the fluorine doped amorphous carbon layer; dry etching contact holes in the PMD layer to expose the fluorine doped amorphous carbon layer; and, removing the fluorine doped amorphous carbon layer according to a dry stripping process.

Abstract translation: 一种包括接触蚀刻停止层和接触孔形成方法的半导体器件，用于减少下面的材料损耗和改进的器件性能，所述方法包括提供包括包括CMOS器件，STI结构和金属硅化物区域的有源区的半导体衬底; 在有源区上形成氟掺杂的非晶碳层; 在氟掺杂的非晶碳层上形成PMD层; 在PMD层中干蚀刻接触孔以暴露氟掺杂的无定形碳层; 并根据干法汽提法除去氟掺杂的无定形碳层。

公开(公告)号：US20060170058A1

公开(公告)日：2006-08-03

申请号：US11048485

申请日：2005-01-31

Applicant: Wen-Chuan Chiang ,  Cheng-Ku Chen ,  Mu-Chi Chiang ,  Min-Hwa Chi

Inventor： Wen-Chuan Chiang ,  Cheng-Ku Chen ,  Mu-Chi Chiang ,  Min-Hwa Chi

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/76829 ,  H01L21/0212 ,  H01L21/02266 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/3127 ,  H01L21/31608 ,  H01L21/31625 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823871 ,  H01L29/78 ,  H01L29/7843 ,  Y02P80/30

Abstract: A semiconductor device including a contact etch stop layer and contact hole formation method for reduced underlying material loss and improved device performance, the method including providing a semiconductor substrate including an active region including a CMOS device, STI structures, and metal silicide regions; forming a fluorine doped amorphous carbon layer over the active region; forming a PMD layer on the fluorine doped amorphous carbon layer; dry etching contact holes in the PMD layer to expose the fluorine doped amorphous carbon layer; and, removing the fluorine doped amorphous carbon layer according to a dry stripping process.

Abstract translation: 一种包括接触蚀刻停止层和接触孔形成方法的半导体器件，用于减少下面的材料损耗和改进的器件性能，所述方法包括提供包括包括CMOS器件，STI结构和金属硅化物区域的有源区的半导体衬底; 在有源区上形成氟掺杂的非晶碳层; 在氟掺杂的非晶碳层上形成PMD层; 在PMD层中干蚀刻接触孔以暴露氟掺杂的无定形碳层; 并根据干法汽提法除去氟掺杂的无定形碳层。

公开(公告)号：US06500727B1

公开(公告)日：2002-12-31

申请号：US09957423

申请日：2001-09-21

Applicant: Cheng-Ku Chen ,  Fang-Cheng Chen ,  Hun-Jan Tao

Inventor： Cheng-Ku Chen ,  Fang-Cheng Chen ,  Hun-Jan Tao

IPC: H01L2176

CPC classification number: H01L21/76232 ,  Y10S148/05

Abstract: A method for forming a trench having upper rounded corners comprising the following steps. A substrate having an oxide layer formed thereover is provided. A hard mask layer is formed over the oxide layer. A patterned patterning layer is formed over the hard mask layer leaving one or more portions of the hard mask layer exposed. The hard mask layer is patterned using the patterned patterning layer as a mask to form a patterned hard mask layer having one or more openings exposing one or more portions of the oxide layer. The patterned patterning layer is removed. The oxide layer is patterned using the patterned hard mask layer as a mask using a first trench etching process to etch through the oxide layer at the one or more exposed portions of the oxide layer and into the substrate to form one or more shallow trenches within the substrate having upper rounded corners at the respective interfaces between substrate and patterned oxide layer. The substrate is further etched at the one or more shallow trenches using a second trench etching process to form one or more completed trenches having the upper rounded corners at the respective interfaces between substrate and patterned oxide layer.

Abstract translation: 一种用于形成具有上圆角的沟槽的方法，包括以下步骤。 提供了具有形成在其上的氧化物层的衬底。 在氧化物层上形成硬掩模层。 在硬掩模层之上形成图案化图案层，留下硬掩模层的一个或多个部分露出。 使用图案化图案化层作为掩模对硬掩模层进行构图，以形成具有暴露氧化物层的一个或多个部分的一个或多个开口的图案化硬掩模层。 去除图案化图案层。 使用第一沟槽蚀刻工艺，使用图案化的硬掩模层作为掩模来对氧化物层进行图案化，以蚀刻通过氧化物层的一个或多个暴露部分处的氧化物层并进入衬底，以在衬底内形成一个或多个浅沟槽 衬底在衬底和图案化氧化物层之间的相应界面处具有上圆角。 使用第二沟槽蚀刻工艺在一个或多个浅沟槽处进一步蚀刻衬底，以形成在衬底和图案化氧化物层之间的相应界面处具有上圆角的一个或多个完成的沟槽。

公开(公告)号：US07129140B2

公开(公告)日：2006-10-31

申请号：US10798178

申请日：2004-03-11

Applicant: Cheng-Ku Chen ,  Min-Hwa Chi

Inventor： Cheng-Ku Chen ,  Min-Hwa Chi

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/6659

Abstract: Methods of forming MOSFET devices featuring LDD regions offset from the edges of conductive gate structures has been developed. A first embodiment of this invention features the definition of a tapered conductive gate structure with the foot of the tapered structure larger in width than the top of the structure. Formation of an LDD region is accomplished in regions of the semiconductor substrate not covered by the tapered conductive structure. A dry etch procedure is next used to remove the foot of the tapered conductive structure resulting in an LDD region being offset from the edges of a now straight walled conductive structure. A second embodiment of this invention entails the definition of a conductive gate structure featuring notches located at the bottom of the conductive gate structure, extending inwards. Formation of an LDD region is again accomplished in regions of the semiconductor substrate not underlying the non-notched portion of the conductive gate structure, resulting in the LDD region being offset from the notched edges of the conductive gate structure.

Abstract translation: 已经开发了形成具有从导电栅极结构的边缘偏移的LDD区域的MOSFET器件的方法。 本发明的第一实施例的特征在于锥形导电栅极结构的定义，其中锥形结构的底部宽度大于结构的顶部。 在半导体衬底的未被锥形导电结构覆盖的区域中实现LDD区的形成。 接下来使用干蚀刻工艺去除锥形导电结构的脚，导致LDD区域从现在的直壁导电结构的边缘偏移。 本发明的第二实施例需要定义导电栅极结构，其特征在于位于导电栅结构底部的向内延伸的凹口。 LDD区域的形成再次在半导体衬底的不在导电栅极结构的非凹口部分下方的区域中实现，导致LDD区域偏离导电栅极结构的缺口边缘。

公开(公告)号：US20060205207A1

公开(公告)日：2006-09-14

申请号：US11075777

申请日：2005-03-08

Applicant: Cheng-Ku Chen ,  Min-Hwa Chi

Inventor： Cheng-Ku Chen ,  Min-Hwa Chi

IPC: H01L21/4763

CPC classification number: H01L21/76811 ,  H01L21/76808 ,  H01L21/76813

Abstract: A method for forming a dual damascene with improved profiles including providing a semiconductor process wafer including a dielectric insulating layer and an overlying hardmask layer; forming an uppermost layer of amorphous carbon substantially conformally over the hardmask layer; forming a trench line opening through at least the thickness of the amorphous carbon layer; forming a dual damascene opening comprising forming the trench line opening overlying a via opening pattern through a thickness of the hardmask layer and partially through a thickness of the dielectric insulating layer; and, filling the dual damascene opening with metal.

Abstract translation: 一种用于形成具有改进轮廓的双镶嵌的方法，包括提供包括介电绝缘层和覆盖硬掩模层的半导体工艺晶片; 基本上保形地在硬掩模层上形成无定形碳的最上层; 通过至少所述无定形碳层的厚度形成沟槽线开口; 形成双镶嵌开口，包括形成覆盖通孔开口图案的沟槽线开口，穿过硬掩模层的厚度并且部分地穿过介电绝缘层的厚度; 并用金属填充双镶嵌开口。

公开(公告)号：US06787455B2

公开(公告)日：2004-09-07

申请号：US10032353

申请日：2001-12-21

Applicant: Ming-Huan Tsai ,  Hun-Jan Tao ,  Ju-Wang Hsu ,  Cheng-Ku Chen

Inventor： Ming-Huan Tsai ,  Hun-Jan Tao ,  Ju-Wang Hsu ,  Cheng-Ku Chen

IPC: H01L214763

CPC classification number: G03F7/094 ,  H01L21/0274 ,  H01L21/76802

Abstract: A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist over the non-silicon containing photoresist layer; exposing said silicon containing photoresist layer to an activating light source an exposure surface defined by an overlying pattern according to a photolithographic process; developing said silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least oxygen, carbon monoxide, and argon.

Abstract translation: 一种使用双层光致抗蚀剂的半导体器件特征显影的方法，包括在衬底上提供不含硅的光致抗蚀剂层; 在含硅光致抗蚀剂层上提供含硅光致抗蚀剂; 将所述含硅光致抗蚀剂层暴露于激活光源，根据光刻工艺由覆盖图案限定的曝光表面; 根据光刻工艺显影所述含硅光致抗蚀剂层以露出含有非硅的光致抗蚀剂层的一部分; 以及通过从包括至少氧，一氧化碳和氩的环境混合物点燃等离子体，在等离子体反应器中干燥显影所述不含硅的光致抗蚀剂层。