公开(公告)号：US06784115B1

公开(公告)日：2004-08-31

申请号：US09216078

申请日：1998-12-18

申请人： Cheng-Tsung Ni ,  Jacson Liu ,  Chih-Sheng Chang ,  Hudy-Jong Wu

发明人： Cheng-Tsung Ni ,  Jacson Liu ,  Chih-Sheng Chang ,  Hudy-Jong Wu

IPC分类号： H01L218246

CPC分类号： H01L27/11526 ,  H01L21/2822 ,  H01L21/28273 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/11253 ,  H01L27/115 ,  H01L27/11546 ,  H01L27/118 ,  H01L29/66825 ,  Y10S438/911

摘要： Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (160) that is thin in some regions, such as the cell region, and thicker in other regions (165), such as the periphery region. The method simultaneously provides a gate oxide layer with two or more thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to a specific embodiment of the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor ROM device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor ROM device.

摘要翻译： 改进的制造半导体集成电路器件的方法，特别是闪存EEPROM器件。 根据一个实施例，本发明提供一种形成半导体器件的方法，所述半导体器件具有栅极氧化物层（160），所述栅极氧化物层（160）在诸如电池区域的某些区域中较薄，并且在其它区域（165） 地区。 该方法同时提供具有两个或多个厚度的栅极氧化物层，而没有使用具有蚀刻步骤的使用含污染物的光致抗蚀剂的现有技术方法的厚度控制问题。 根据本发明的具体实施例，栅极氧化物具有足够薄的第一厚度以为半导体ROM器件提供高驱动能力，并且第二厚度足够厚以提供半导体ROM器件的高电压可靠性 。

公开(公告)号：US6127699A

公开(公告)日：2000-10-03

申请号：US371378

申请日：1999-08-10

申请人： Cheng-Tsung Ni ,  Chih-Hsun Chu

发明人： Cheng-Tsung Ni ,  Chih-Hsun Chu

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66613 ,  H01L29/66621 ,  H01L29/7834 ,  H01L21/2257

摘要： A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming a lightly doped region in each active area; forming a heavily doped p-Si (or a-Si) layer; depositing and patterning several dielectric layers to form a gate area surrounded by vertical spacers; forming a groove in the gate area and the substrate; forming a gate oxide layer in the groove and driving dopants in the doped p-Si (or a-Si) layer into the substrate to form the source and the drain; and forming a gate electrode in the groove.

摘要翻译： 一种用于制造半导体器件的方法，该半导体器件包括具有增加的有效栅极长度的源极，漏极和栅电极。 通过包括以下步骤的方法制造半导体器件：形成由场氧化物区域分离的有源区域; 在每个有效区域中形成轻掺杂区域; 形成重掺杂的p-Si（或a-Si）层; 沉积和图形化几个电介质层以形成由垂直间隔物包围的栅极区域; 在栅极区域和衬底中形成沟槽; 在沟槽中形成栅极氧化层，并将掺杂的p-Si（或a-Si）层中的掺杂剂驱动到衬底中以形成源极和漏极; 以及在沟槽中形成栅电极。

公开(公告)号：US06888197B2

公开(公告)日：2005-05-03

申请号：US10668434

申请日：2003-09-22

申请人： Cheng-Tsung Ni ,  Jen-Te Chen

发明人： Cheng-Tsung Ni ,  Jen-Te Chen

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L31/119 ,  H01L31/113 ,  H01L31/062 ,  H01L29/94 ,  H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0696

摘要： A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions extending from the base portion, and a plurality of photo-resist regions. Each of the cells is geometrically configured with the base portion and the plurality of protruding portions defining a closed cell boundary enclosing each of said cells. The cells are formed over the substrate, and the closed cell boundaries of the cells are arranged regularly with each other with no overlapping among the cells. The base portions are disposed in a matrix arrangement having rows and columns. The base portions are oriented from end to end in a direction of the columns and the protruding portions extend from the base portions along a direction of the rows. The photo-resist regions cover the base portions on the same column. None of the protruding portions are disposed between the base portions on the same column. The cells are doped with N type dopants by using the photo-resist regions as masks.

摘要翻译： 根据本发明的一个实施例的功率MOSFET布局包括衬底和多个单元。 每个单元包括基部，从基部延伸的多个突出部分和多个光致抗蚀剂区域。 每个单元几何地配置有基部，并且多个突出部分限定封闭每个所述单元的封闭单元边界。 细胞形成在衬底上，并且细胞的闭孔边界彼此规则地排列，在细胞之间不重叠。 基部以具有行和列的矩阵布置设置。 基部沿着列的方向从端部到端部定向，并且突出部分沿着行的方向从基部延伸。 光致抗蚀剂区覆盖同一列上的基部。 没有突出部分设置在同一列的基部之间。 通过使用光致抗蚀剂区域作为掩模，将这些单元掺杂有N型掺杂剂。