公开(公告)号：US5972754A

公开(公告)日：1999-10-26

申请号：US95674

申请日：1998-06-10

申请人： Cheng-Tsung Ni ,  Chih-Hsun Chu

发明人： Cheng-Tsung Ni ,  Chih-Hsun Chu

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66613 ,  H01L29/66621 ,  H01L29/7834 ,  H01L21/2257

摘要： A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming a lightly doped region in each active area; forming a heavily doped p-Si (or a-Si) layer; depositing and patterning several dielectric layers to form a gate area surrounded by vertical spacers; forming a groove in the gate area and the substrate; forming a gate oxide layer in the groove and driving dopants in the doped p-Si (or a-Si) layer into the substrate to form the source and the drain; and forming a gate electrode in the groove.

公开(公告)号：US6127699A

公开(公告)日：2000-10-03

申请号：US371378

申请日：1999-08-10

申请人： Cheng-Tsung Ni ,  Chih-Hsun Chu

发明人： Cheng-Tsung Ni ,  Chih-Hsun Chu

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66613 ,  H01L29/66621 ,  H01L29/7834 ,  H01L21/2257

摘要： A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming a lightly doped region in each active area; forming a heavily doped p-Si (or a-Si) layer; depositing and patterning several dielectric layers to form a gate area surrounded by vertical spacers; forming a groove in the gate area and the substrate; forming a gate oxide layer in the groove and driving dopants in the doped p-Si (or a-Si) layer into the substrate to form the source and the drain; and forming a gate electrode in the groove.

摘要翻译： 一种用于制造半导体器件的方法，该半导体器件包括具有增加的有效栅极长度的源极，漏极和栅电极。 通过包括以下步骤的方法制造半导体器件：形成由场氧化物区域分离的有源区域; 在每个有效区域中形成轻掺杂区域; 形成重掺杂的p-Si（或a-Si）层; 沉积和图形化几个电介质层以形成由垂直间隔物包围的栅极区域; 在栅极区域和衬底中形成沟槽; 在沟槽中形成栅极氧化层，并将掺杂的p-Si（或a-Si）层中的掺杂剂驱动到衬底中以形成源极和漏极; 以及在沟槽中形成栅电极。

公开(公告)号：US6008106A

公开(公告)日：1999-12-28

申请号：US915693

申请日：1997-08-21

申请人： Tuby Tu ,  Chen Kuang-Chao ,  Cheng-Tsung Ni ,  Chih-Hsun Chu

发明人： Tuby Tu ,  Chen Kuang-Chao ,  Cheng-Tsung Ni ,  Chih-Hsun Chu

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/7621

摘要： A method of forming isolation region of an integrated circuit by using rough oxide mask is described. First, a layer of first dielectric is formed on the surface of a silicon substrate. The first dielectric layer is then patterned to define active device region and isolation region. Next, a very thin layer of silicon dioxide is formed over the silicon substrate surface, followed by depositing a layer of rough oxide with proper grain size overlaying the silicon dioxide layer. By using rough oxide grains as an etching mask, the silicon dioxide layer and the silicon substrate underneath are spontaneously etched to form multiple trenches in the isolation region. Next, the rough oxide grains and silicon dioxide layers are stripped. Then, filed oxidation is performed to complete the field oxide isolation formation.

摘要翻译： 描述了通过使用粗略氧化物掩膜形成集成电路的隔离区域的方法。 首先，在硅衬底的表面上形成第一电介质层。 然后将第一介电层图案化以限定有源器件区域和隔离区域。 接下来，在硅衬底表面上形成非常薄的二氧化硅层，随后沉积具有覆盖二氧化硅层的适当晶粒尺寸的粗大氧化物层。 通过使用粗糙氧化物晶粒作为蚀刻掩模，自发蚀刻下面的二氧化硅层和硅衬底，以在隔离区域中形成多个沟槽。 接下来，剥离粗糙的氧化物颗粒和二氧化硅层。 然后进行归档氧化以完成场氧化物隔离层。

公开(公告)号：US06888197B2

公开(公告)日：2005-05-03

申请号：US10668434

申请日：2003-09-22

申请人： Cheng-Tsung Ni ,  Jen-Te Chen

发明人： Cheng-Tsung Ni ,  Jen-Te Chen

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L31/119 ,  H01L31/113 ,  H01L31/062 ,  H01L29/94 ,  H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0696

摘要： A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions extending from the base portion, and a plurality of photo-resist regions. Each of the cells is geometrically configured with the base portion and the plurality of protruding portions defining a closed cell boundary enclosing each of said cells. The cells are formed over the substrate, and the closed cell boundaries of the cells are arranged regularly with each other with no overlapping among the cells. The base portions are disposed in a matrix arrangement having rows and columns. The base portions are oriented from end to end in a direction of the columns and the protruding portions extend from the base portions along a direction of the rows. The photo-resist regions cover the base portions on the same column. None of the protruding portions are disposed between the base portions on the same column. The cells are doped with N type dopants by using the photo-resist regions as masks.

摘要翻译： 根据本发明的一个实施例的功率MOSFET布局包括衬底和多个单元。 每个单元包括基部，从基部延伸的多个突出部分和多个光致抗蚀剂区域。 每个单元几何地配置有基部，并且多个突出部分限定封闭每个所述单元的封闭单元边界。 细胞形成在衬底上，并且细胞的闭孔边界彼此规则地排列，在细胞之间不重叠。 基部以具有行和列的矩阵布置设置。 基部沿着列的方向从端部到端部定向，并且突出部分沿着行的方向从基部延伸。 光致抗蚀剂区覆盖同一列上的基部。 没有突出部分设置在同一列的基部之间。 通过使用光致抗蚀剂区域作为掩模，将这些单元掺杂有N型掺杂剂。

公开(公告)号：US06660592B2

公开(公告)日：2003-12-09

申请号：US10160299

申请日：2002-05-29

申请人： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

发明人： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/7802

摘要： Embodiment of the present invention are directed to improving the performance of a DMOS transistor. A method of fabricating a DMOS transistor comprises providing a semiconductor substrate having a gate oxide and a trenched gate, and implanting first conductive dopants into a surface of the semiconductor substrate adjacent to the trenched gate to form a first doping region. An insulating layer is deposited over the semiconductor substrate; and selectively etching the insulating layer to form a source contact window over a central portion of the first doping region and to leave an insulator structure above the trenched gate. The source contact window of the insulating layer has an enlarged top portion which is larger in size than a bottom portion of the source contact window closer to the first doping region than the enlarged top portion. The enlarged top portion is typically bowl-shaped. Second conductive dopants are implanted through the source contact window to form a second doping region in the central portion of the first doping region.

公开(公告)号：US06228729B1

公开(公告)日：2001-05-08

申请号：US09514455

申请日：2000-02-25

申请人： Cheng-Tsung Ni

发明人： Cheng-Tsung Ni

IPC分类号： H01L21336

CPC分类号： H01L29/66628 ,  H01L21/76838 ,  H01L21/76877 ,  H01L29/66545

摘要： A process for fabricating a semiconductor device comprising a gate electrode, a raised source, a raised drain and an interconnect inlaid into an isolation region. A semiconductor device is fabricated by a process comprising the following steps: forming sequentially a first dielectric layer and a first conductor layer on the substrate; forming one or more inset isolation regions in the substrate; filling each inset isolation region with an isolation layer; forming a second dielectric layer on top of the first conductor layer and the isolation layers; forming simultaneously a first and a second trench; forming a plurality of cavities at the bottom of the first trench; filling each cavity with a second conductor layer; forming a plurality of dielectric sidewalls and a dielectric bottom layer in the first trench; forming the gate electrode and the interconnect by filling the first and second trenches with a third conductor layer; doping the first conductor layer with dopants; and forming the raised source and the raised drain by driving the dopants into the surface region of the substrate.

摘要翻译： 一种用于制造半导体器件的方法，该半导体器件包括嵌入到隔离区中的栅电极，凸起源，升高漏极和互连。 通过包括以下步骤的方法制造半导体器件：在衬底上依次形成第一电介质层和第一导体层; 在衬底中形成一个或多个插入隔离区; 用隔离层填充每个插入隔离区; 在所述第一导体层和隔离层的顶部上形成第二电介质层; 同时形成第一和第二沟槽; 在第一沟槽的底部形成多个空腔; 用第二导体层填充每个空腔; 在所述第一沟槽中形成多个电介质侧壁和电介质底层; 通过用第三导体层填充第一和第二沟槽来形成栅电极和互连; 用掺杂剂掺杂第一导体层; 以及通过将掺杂剂驱动到衬底的表面区域中而形成升高的源极和高的漏极。

公开(公告)号：US06784115B1

公开(公告)日：2004-08-31

申请号：US09216078

申请日：1998-12-18

申请人： Cheng-Tsung Ni ,  Jacson Liu ,  Chih-Sheng Chang ,  Hudy-Jong Wu

发明人： Cheng-Tsung Ni ,  Jacson Liu ,  Chih-Sheng Chang ,  Hudy-Jong Wu

IPC分类号： H01L218246

CPC分类号： H01L27/11526 ,  H01L21/2822 ,  H01L21/28273 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/11253 ,  H01L27/115 ,  H01L27/11546 ,  H01L27/118 ,  H01L29/66825 ,  Y10S438/911

摘要： Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (160) that is thin in some regions, such as the cell region, and thicker in other regions (165), such as the periphery region. The method simultaneously provides a gate oxide layer with two or more thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to a specific embodiment of the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor ROM device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor ROM device.

摘要翻译： 改进的制造半导体集成电路器件的方法，特别是闪存EEPROM器件。 根据一个实施例，本发明提供一种形成半导体器件的方法，所述半导体器件具有栅极氧化物层（160），所述栅极氧化物层（160）在诸如电池区域的某些区域中较薄，并且在其它区域（165） 地区。 该方法同时提供具有两个或多个厚度的栅极氧化物层，而没有使用具有蚀刻步骤的使用含污染物的光致抗蚀剂的现有技术方法的厚度控制问题。 根据本发明的具体实施例，栅极氧化物具有足够薄的第一厚度以为半导体ROM器件提供高驱动能力，并且第二厚度足够厚以提供半导体ROM器件的高电压可靠性 。

公开(公告)号：US06821913B2

公开(公告)日：2004-11-23

申请号：US10232260

申请日：2002-08-29

申请人： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

发明人： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

IPC分类号： H01L2131

CPC分类号： H01L29/66734 ,  H01L21/0274 ,  H01L21/76224 ,  H01L29/42368

摘要： Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defining the mask oxide layer to form a patterned mask oxide layer and exposing a partial surface of the substrate to form a window; and using the patterned mask oxide layer as an etching mask to form the trench in the window. A first oxide layer is formed on the sidewall and the bottom of the trench of the substrate. A photoresist layer is formed on the substrate, filling the trench of the substrate. The method further comprises partially etching back the photoresist layer to leave a remaining photoresist layer in the trench. The height of the remaining photoresist layer is lower than the depth of the trench. A curing treatment of the remaining photoresist layer is performed after the partial etching. The patterned mask oxide layer and a portion of the first oxide layer are removed to leave a remaining first oxide layer at the bottom of the trench. The remaining photoresist layer is removed. A second oxide layer is formed on the substrate covering at least the remaining first oxide layer to form the dual oxide layers at the bottom of the trench.

摘要翻译： 本发明的实施例涉及一种用于在衬底的沟槽的底部形成双重氧化物层的改进方法。 衬底具有包括底部和侧壁的沟槽。 可以通过在衬底上形成掩模氧化物层来形成沟槽; 限定所述掩模氧化物层以形成图案化掩模氧化物层并暴露所述衬底的部分表面以形成窗口; 并且使用图案化的掩模氧化物层作为蚀刻掩模以在窗口中形成沟槽。 第一氧化物层形成在衬底的沟槽的侧壁和底部上。 在衬底上形成光刻胶层，填充衬底的沟槽。 该方法还包括部分地蚀刻光致抗蚀剂层以在沟槽中留下残留的光致抗蚀剂层。 剩余的光致抗蚀剂层的高度低于沟槽的深度。 在部分蚀刻之后进行剩余光致抗蚀剂层的固化处理。 图案化的掩模氧化物层和第一氧化物层的一部分被去除以在沟槽的底部留下剩余的第一氧化物层。 去除剩余的光致抗蚀剂层。 在衬底上形成第二氧化物层，至少覆盖剩余的第一氧化物层，以在沟槽的底部形成双氧化层。

公开(公告)号：US06657263B2

公开(公告)日：2003-12-02

申请号：US09896205

申请日：2001-06-28

申请人： Cheng-Tsung Ni

发明人： Cheng-Tsung Ni

IPC分类号： H01L2976

CPC分类号： H01L29/66628 ,  H01L21/76838 ,  H01L21/76877 ,  H01L29/66545 ,  H01L29/7834

摘要： A method of fabricating an IC device on a substrate comprising MOS transistors and other IC components. Each of the transistors of the IC device comprises a raised source electrode, a raised drain electrode, dual gate electrodes and self-aligned interconnect contact windows, and is connected to other transistors and other IC components through interconnects formed on top of such self-aligned contact windows.

摘要翻译： 一种在包括MOS晶体管和其它IC组件的衬底上制造IC器件的方法。 IC器件的每个晶体管包括升高的源电极，升高的漏电极，双栅极电极和自对准的互连接触窗口，并且通过在这样的自对准顶部上形成的互连而连接到其它晶体管和其它IC部件 联系窗口。

公开(公告)号：US06563166B1

公开(公告)日：2003-05-13

申请号：US09523064

申请日：2000-03-10

申请人： Cheng-Tsung Ni

发明人： Cheng-Tsung Ni

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A memory device includes a first memory cell and a second memory cell both controlled by a common control gate. The device includes: a substrate; first and second stacks each including an insulating layer formed over the substrate, a first conductive layer formed over the insulating layer and providing a select gate, and a first dielectric layer formed over the first conductive layer, each of the stacks also including an inner sidewall and an outer sidewall, the. stacks being separated by a common area of the substrate, the inner and outer sidewalls of the stacks being coated with a second dielectric layer; first and second spacers formed adjacent the inner sidewalls of the first and second stacks respectively, the first and second spacers being separated by a medial portion of the common source area of the substrate, each of the spacers. including a tunnel oxide layer disposed over the substrate, and a second conductive layer disposed over the tunnel oxide layer and providing a floating gate; first and second drain regions formed in the substrate proximate the outer sidewalls of the first and second stacks; a common source region formed beneath the common source area; a third dielectric layer disposed over the first and second spacers, and the first and second stacks; and a third conductive layer, disposed over inner portions of the first and second select gate stacks, and forming the common control gate.

摘要翻译： 存储器件包括由公共控制栅极控制的第一存储器单元和第二存储单元。 该装置包括：基板; 第一和第二堆叠，每个堆叠包括形成在衬底上的绝缘层，形成在绝缘层上并提供选择栅极的第一导电层和形成在第一导电层上的第一电介质层，每个堆叠还包括内侧壁 和外侧壁。 堆叠由衬底的公共区域分开，堆叠的内侧壁和外侧壁涂覆有第二介电层; 分别与第一和第二堆叠的内侧壁相邻形成的第一和第二间隔件，第一和第二间隔件被衬底的公共源区域的中间部分分隔开，每个间隔件。 包括设置在所述衬底上的隧道氧化物层，以及设置在所述隧道氧化物层上并提供浮动栅极的第二导电层; 形成在靠近第一和第二堆叠的外侧壁的基板中的第一和第二漏极区域; 形成在共同源极区域下面的共同源极区域; 设置在第一和第二间隔物上的第三电介质层，以及第一和第二堆叠; 以及第三导电层，设置在第一和第二选择栅极堆叠的内部部分上，并形成公共控制栅极。