公开(公告)号：US6008106A

公开(公告)日：1999-12-28

申请号：US915693

申请日：1997-08-21

申请人： Tuby Tu ,  Chen Kuang-Chao ,  Cheng-Tsung Ni ,  Chih-Hsun Chu

发明人： Tuby Tu ,  Chen Kuang-Chao ,  Cheng-Tsung Ni ,  Chih-Hsun Chu

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/7621

摘要： A method of forming isolation region of an integrated circuit by using rough oxide mask is described. First, a layer of first dielectric is formed on the surface of a silicon substrate. The first dielectric layer is then patterned to define active device region and isolation region. Next, a very thin layer of silicon dioxide is formed over the silicon substrate surface, followed by depositing a layer of rough oxide with proper grain size overlaying the silicon dioxide layer. By using rough oxide grains as an etching mask, the silicon dioxide layer and the silicon substrate underneath are spontaneously etched to form multiple trenches in the isolation region. Next, the rough oxide grains and silicon dioxide layers are stripped. Then, filed oxidation is performed to complete the field oxide isolation formation.

摘要翻译： 描述了通过使用粗略氧化物掩膜形成集成电路的隔离区域的方法。 首先，在硅衬底的表面上形成第一电介质层。 然后将第一介电层图案化以限定有源器件区域和隔离区域。 接下来，在硅衬底表面上形成非常薄的二氧化硅层，随后沉积具有覆盖二氧化硅层的适当晶粒尺寸的粗大氧化物层。 通过使用粗糙氧化物晶粒作为蚀刻掩模，自发蚀刻下面的二氧化硅层和硅衬底，以在隔离区域中形成多个沟槽。 接下来，剥离粗糙的氧化物颗粒和二氧化硅层。 然后进行归档氧化以完成场氧化物隔离层。

公开(公告)号：US6127699A

公开(公告)日：2000-10-03

申请号：US371378

申请日：1999-08-10

申请人： Cheng-Tsung Ni ,  Chih-Hsun Chu

发明人： Cheng-Tsung Ni ,  Chih-Hsun Chu

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66613 ,  H01L29/66621 ,  H01L29/7834 ,  H01L21/2257

摘要： A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming a lightly doped region in each active area; forming a heavily doped p-Si (or a-Si) layer; depositing and patterning several dielectric layers to form a gate area surrounded by vertical spacers; forming a groove in the gate area and the substrate; forming a gate oxide layer in the groove and driving dopants in the doped p-Si (or a-Si) layer into the substrate to form the source and the drain; and forming a gate electrode in the groove.

摘要翻译： 一种用于制造半导体器件的方法，该半导体器件包括具有增加的有效栅极长度的源极，漏极和栅电极。 通过包括以下步骤的方法制造半导体器件：形成由场氧化物区域分离的有源区域; 在每个有效区域中形成轻掺杂区域; 形成重掺杂的p-Si（或a-Si）层; 沉积和图形化几个电介质层以形成由垂直间隔物包围的栅极区域; 在栅极区域和衬底中形成沟槽; 在沟槽中形成栅极氧化层，并将掺杂的p-Si（或a-Si）层中的掺杂剂驱动到衬底中以形成源极和漏极; 以及在沟槽中形成栅电极。

公开(公告)号：US5972754A

公开(公告)日：1999-10-26

申请号：US95674

申请日：1998-06-10

申请人： Cheng-Tsung Ni ,  Chih-Hsun Chu

发明人： Cheng-Tsung Ni ,  Chih-Hsun Chu

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66613 ,  H01L29/66621 ,  H01L29/7834 ,  H01L21/2257

摘要： A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming a lightly doped region in each active area; forming a heavily doped p-Si (or a-Si) layer; depositing and patterning several dielectric layers to form a gate area surrounded by vertical spacers; forming a groove in the gate area and the substrate; forming a gate oxide layer in the groove and driving dopants in the doped p-Si (or a-Si) layer into the substrate to form the source and the drain; and forming a gate electrode in the groove.

公开(公告)号：US08969827B2

公开(公告)日：2015-03-03

申请号：US13544019

申请日：2012-07-09

申请人： Yong-Fen Hsieh ,  Chih-Hsun Chu ,  Pradeep Sharma ,  Yu-Feng Ko ,  Chung-Shi Yang ,  Lin-Ai Tai ,  Yu-Ching Chen

发明人： Yong-Fen Hsieh ,  Chih-Hsun Chu ,  Pradeep Sharma ,  Yu-Feng Ko ,  Chung-Shi Yang ,  Lin-Ai Tai ,  Yu-Ching Chen

IPC分类号： B82Y35/00 ,  G01N1/40 ,  G01N23/02 ,  G01N33/49

CPC分类号： H01J37/261 ,  B01L3/508 ,  B01L2200/0678 ,  B01L2300/0822 ,  G01N1/28 ,  G01N1/4022 ,  G01N23/02 ,  G01N2001/4027 ,  H01J37/16 ,  H01J37/20 ,  H01J37/222 ,  H01J37/3178 ,  H01J2237/2007 ,  H01J2237/2602 ,  H01J2237/2802

摘要： A specimen kit having a tiny chamber is disclosed for a specimen preparation for TEM. The space height of the chamber is far smaller than dimensions of blood cells and therefore is adapted to sort nanoparticles from the blood cells. The specimen prepared under this invention is suitable for TEM observation over a true distribution status of nanoparticles in blood. The extremely tiny space height in Z direction eliminates the possibility of aggregation of the nanoparticles and/or agglomeration in Z direction during drying; therefore, a specimen prepared under this invention is suitable for TEM observation over the dispersion and/or agglomeration of nanoparticles in a blood.

摘要翻译： 公开了一种用于TEM的样品制备的具有微小室的标本试剂盒。 室的空间高度远小于血细胞的尺寸，因此适于从血细胞分选纳米颗粒。 根据本发明制备的样品适用于在血液中纳米颗粒的真实分布状态的TEM观察。 在Z方向极微小的空间高度消除了在干燥过程中纳米颗粒聚集和/或Z方向附聚的可能性; 因此，根据本发明制备的样品适用于在血液中纳米颗粒的分散和/或附聚的TEM观察。

公开(公告)号：US5926712A

公开(公告)日：1999-07-20

申请号：US753216

申请日：1996-11-21

申请人： Min-Liang Chen ,  Chih-Hsien Wang ,  Chih-Hsun Chu ,  San-Jung Chang

发明人： Min-Liang Chen ,  Chih-Hsien Wang ,  Chih-Hsun Chu ,  San-Jung Chang

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10

CPC分类号： H01L29/66537 ,  H01L29/1083 ,  H01L29/6659 ,  H01L21/26586

摘要： The present invention is related to a process for fabricating a MOS device having a short channel. The process according to the present invention includes the steps of (a) providing a semiconductor substrate and forming a gate structure on the semiconductor substrate; (b) implanting impurities of a first charge type to the semiconductor substrate with the gate structure serving as a mask to form a first source/drain region having a predetermined impurity concentration; (c) pocket-implanting impurities of a second charge type to the resulting semiconductor substrate with the gate structure serving as a mask to form a second source/drain region having a predetermined impurity concentration; and (d) forming a gate side wall on a flank of the gate structure, and implanting impurities of the first charge type to the resulting semiconductor substrate with the gate structure and the gate side wall serving as a mask to form a third source/drain region having a predetermined impurity concentration. The present invention is characterized in that no threshold voltage adjustment implantation to the semiconductor substrate is needed prior to the growth of the gate structure, and in stead, the diffusion ability of the pocket-implanted impurities in the step (c) can concurrently adjust the threshold voltage of the device.

摘要翻译： 本发明涉及制造具有短通道的MOS器件的工艺。 根据本发明的方法包括以下步骤：（a）提供半导体衬底并在半导体衬底上形成栅极结构; （b）以栅极结构作为掩模将半导体衬底中的第一种类型的杂质注入到半导体衬底中，形成具有预定杂质浓度的第一源/漏区; （c）以所述栅极结构作为掩模将所述第二电荷型杂质注入所得的半导体衬底，以形成具有预定杂质浓度的第二源/漏区; 以及（d）在所述栅极结构的侧面上形成栅极侧壁，并且以所述栅极结构和所述栅极侧壁用作掩模，将所述第一电荷类型的杂质注入所得半导体衬底，以形成第三源极/漏极 区域具有预定的杂质浓度。 本发明的特征在于，在栅极结构生长之前，不需要对半导体衬底进行阈值电压调整注入，而是步骤（c）中的注入袋的杂质的扩散能力可以同时调节 器件的阈值电压。

公开(公告)号：US07462545B2

公开(公告)日：2008-12-09

申请号：US11162727

申请日：2005-09-21

申请人： Jih-Wen Chou ,  Chih-Hsun Chu

发明人： Jih-Wen Chou ,  Chih-Hsun Chu

IPC分类号： H01L21/336

CPC分类号： H01L29/0653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate structure, and a channel region is formed between the source region and the drain region underneath the gate structure. The pair of dielectric barrier layers is respectively formed in the substrate underneath the gate structure between the source region and the drain region. The dielectric barrier layers are used for reducing the drain induced barrier lowering effect in a nanometer scale device.

摘要翻译： 提供半导体器件。 半导体器件具有栅极结构，源极区，漏极区和一对介电阻挡层。 栅极结构形成在基板上。 源极区域和漏极区域形成在栅极结构旁边的衬底中，并且在栅极结构之下的源极区域和漏极区域之间形成沟道区域。 一对电介质阻挡层分别形成在源极区域和漏极区域之间的栅极结构下方的衬底中。 电介质阻挡层用于在纳米级装置中降低漏极引发的阻挡层降低效果。

公开(公告)号：US20080268646A1

公开(公告)日：2008-10-30

申请号：US12168748

申请日：2008-07-07

申请人： Douglas Blaine Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

发明人： Douglas Blaine Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

IPC分类号： H01L21/311

CPC分类号： H01L27/10867 ,  H01L27/0207

摘要： A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of the memory cell and a second orthogonally oriented pattern to define a second portion of the active region of the memory cell thereby creating a ladder shaped active region for a column of the memory cells.

摘要翻译： 一种缩小面积动态随机存取存储器（DRAM）单元及其制造方法，其中通过沿着第一图案形成侧壁间隔物，通过两个光刻间距占据小于一个光刻间距的区域，以限定活动的第一部分 存储单元的区域和第二正交定向图案，以限定存储单元的有源区域的第二部分，从而为存储单元的列创建梯形有源区域。

公开(公告)号：US06952369B2

公开(公告)日：2005-10-04

申请号：US10707562

申请日：2003-12-22

申请人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Jih-Wen Chou ,  Cheng-Tung Huang ,  Chih-Hsun Chu

发明人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Jih-Wen Chou ,  Cheng-Tung Huang ,  Chih-Hsun Chu

IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0475

摘要： A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.

摘要翻译： 一种用于写入存储器模块的方法包括提供多个存储器单元，将第一传输线电压施加到存储器单元的列的第一传输线，将存储单元之间的存储单元的P型通道导通到 写入存储单元的列的第一传输线，关闭存储单元和存储单元的列的第二传输线之间的至少一个存储单元的P型通道，施加字线电压 连接到连接到存储器单元的字线，以便使用带 - 带隧穿将热电子注入存储器单元的第一P型掺杂区域中的结，成为存储单元的氮化硅层 注入，并且将衬底电压施加到多个存储单元的衬底。

公开(公告)号：US06920067B2

公开(公告)日：2005-07-19

申请号：US10248193

申请日：2002-12-25

申请人： Ching-Hsiang Hsu ,  Chih-Hsun Chu ,  Ming-Chou Ho ,  Shih-Jye Shen

发明人： Ching-Hsiang Hsu ,  Chih-Hsun Chu ,  Ming-Chou Ho ,  Shih-Jye Shen

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L27/118 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0408 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/118

摘要： A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+ doped drain region and a first P+ doped source region, the second PMOS transistor includes a single-poly select gate and a second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.

摘要翻译： 芯片上系统（SOC）包含一个内核电路和一个嵌入单个多可擦除可编程只读存储器单元的阵列的输入/输出（I / O）电路，每个存储单元包括串联连接到第二个 PMOS晶体管。 第一和第二PMOS晶体管都形成在P型衬底的N阱上。 第一PMOS晶体管包括单多晶硅浮置栅极，第一P + SUP掺杂漏极区域和第一P + +掺杂源极区域，第二PMOS晶体管包括： 多选择栅极和第二P + +掺杂源极区域，并且第一PMOS晶体管的第一P + +掺杂源极区域用作第二PMOS晶体管的漏极。

公开(公告)号：US06337240B1

公开(公告)日：2002-01-08

申请号：US09237496

申请日：1999-01-25

申请人： Chih-Hsun Chu

发明人： Chih-Hsun Chu

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10873 ,  Y10S438/981

摘要： A method for fabricating an embedded dynamic random access memory (DRAM) is provided. The method contains implanting ions onto the substrate at a DRAM active area and a logic circuit with different dopant concentration. A thermal oxidation process is performed to form a DRAM gate oxide layer with a greater thickness than that of a logic gate oxide layer. A DRAM MOS transistor is formed at a DRAM region and a logic MOS transistor is formed at a logic region. The DRAM MOS transistor has a polycide gate structure. The logic transistor has a first self-aligned silicide (Salicide) layer on its gate structure, and a second Salicide on its interchangeable source/drain region. A dielectric layer is formed over the substrate. A contact opening is formed in the dielectric layer by patterning the dielectric layer to expose the interchangeable source/drain region of the DRAM transistor. A stack capacitor is formed on the dielectric layer.

摘要翻译： 提供了一种制造嵌入式动态随机存取存储器（DRAM）的方法。 该方法包括在DRAM有源区域和具有不同掺杂剂浓度的逻辑电路的衬底上注入离子。 执行热氧化处理以形成具有比逻辑栅极氧化物层的厚度更大的厚度的DRAM栅极氧化物层。 在DRAM区域形成DRAM MOS晶体管，在逻辑区域形成逻辑MOS晶体管。 DRAM MOS晶体管具有多晶硅栅极结构。 逻辑晶体管在其栅极结构上具有第一自对准硅化物（硅化物）层，在其可互换的源极/漏极区上具有第二硅化物。 介电层形成在衬底上。 通过对介电层进行构图以暴露DRAM晶体管的可互换的源极/漏极区域，在电介质层中形成接触开口。 在电介质层上形成堆叠电容器。