公开(公告)号：US20120218503A1

公开(公告)日：2012-08-30

申请号：US13402795

申请日：2012-02-22

Applicant: Chi-Che TSAI ,  Po-Ching LIN ,  Cheng-Ta CHEN ,  Cheng-Chung CHIANG ,  Wei-Yen WU ,  Yen-Hui WU

Inventor： Chi-Che TSAI ,  Po-Ching LIN ,  Cheng-Ta CHEN ,  Cheng-Chung CHIANG ,  Wei-Yen WU ,  Yen-Hui WU

IPC: G02F1/1339 ,  B29C65/48 ,  H05K7/00

CPC classification number: B32B37/26 ,  B29K2105/0079 ,  B32B7/06 ,  B32B37/12 ,  B32B37/18 ,  B32B38/10 ,  B32B38/1858 ,  B32B43/006 ,  B32B2037/268 ,  B32B2307/546 ,  B32B2307/748 ,  B32B2457/20 ,  G02F1/1333 ,  G02F1/133305 ,  G02F1/133514 ,  G02F1/167 ,  G02F2201/50

Abstract: A display including a supporting layer, a flexible layer and a display structure is provided. The display structure has a top side and a bottom side which are opposite to each other. One of the supporting layer and the flexible layer is disposed at the bottom side of the display structure, and the other one of the supporting layer and the flexible layer is disposed at the top side or the bottom side of the display structure. When the supporting layer and the flexible layer are both disposed at the bottom side of the display structure, the flexible layer is located between the supporting layer and the display structure.

Abstract translation: 提供了包括支撑层，柔性层和显示结构的显示器。 显示结构具有彼此相对的顶侧和底侧。 支撑层和柔性层中的一个设置在显示结构的底侧，并且支撑层和柔性层中的另一个设置在显示结构的顶侧或底侧。 当支撑层和柔性层均设置在显示结构的底侧时，柔性层位于支撑层和显示结构之间。

公开(公告)号：US08060676B2

公开(公告)日：2011-11-15

申请号：US11433195

申请日：2006-05-11

Applicant: Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-kuo Kao

Inventor： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-kuo Kao

IPC: G06F13/42 ,  G06F5/06 ,  G06F13/36

CPC classification number: G06F13/423 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

Abstract translation: 本发明提供了一种在总线上热切换数据传输速率的方法，以热切换控制芯片之间的总线的数据传输速率，而无需复位。 当控制芯片之间的总线需要大量的数据传输时，总线被热切换到更高的数据传输速率，以满足数据传输的要求。 相反，当控制芯片之间的总线需要更少的数据传输量时，总线被热切换到较低的数据传输速率以节省功耗。

公开(公告)号：US07051148B2

公开(公告)日：2006-05-23

申请号：US10055558

申请日：2002-01-22

Applicant: Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai ,  Wen-Hao Chuang ,  Chun-Yuan Su

Inventor： Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai ,  Wen-Hao Chuang ,  Chun-Yuan Su

IPC: G06F13/36 ,  G06F13/42

CPC classification number: G06F13/4059

Abstract: A data transmission sequencing method is disclosed. A data read operation from a primary bus to a secondary bus can be executed without having to wait for the complete transfer of write data stored in posted write buffer transferring to the primary bus, as long as the secondary bus is not in use. In the mean time of the primary bus issues a read operation to the secondary bus, the secondary bus can issues write operation to the bridging device when the secondary bus is not in use. Similarly, there is no need to wait for the completion of read operation. With this type of data transmission sequencing mechanism, idle sessions in a conventional transmission sequencing method are eliminated leading to a higher data transmission rate.

公开(公告)号：US06622213B2

公开(公告)日：2003-09-16

申请号：US09881861

申请日：2001-06-15

Applicant: Chau-Chad Tsai ,  Chen-Ping Yang ,  Chi-Che Tsai

Inventor： Chau-Chad Tsai ,  Chen-Ping Yang ,  Chi-Che Tsai

IPC: G06F1300

CPC classification number: G06F12/0846

Abstract: A two-way cache system for interfacing with a peripheral device and a method of operating a two-way cache system for carrying out data transmission between a peripheral device and a memory unit. The cache system has a two-way first-in first-out buffer region and a two-way cache controller. The two-way first-in first-out buffer region further has a first cache data region and a second cache data region. The first cache data region and the second cache data region are capable of holding a batch of first cache data and a batch of second cache data. The two-way cache controller receives a read request from the peripheral device. According to the read request, the requested data and data that ensues or comes after the requested data are retained by the two-way first-in first-out buffer (FIFO) region. If the peripheral device continues to request more data by maintaining a FRAME signal line in an enabled state, the first cache data region and the second cache data region are alternately used to read in subsequent data. A check may be made to see if requested data stored inside the two-way cache buffer region is coherent or consistent with data stored inside the memory unit.

Abstract translation: 一种用于与外围设备进行接口的双向缓存系统和一种操作双向高速缓存系统以在外围设备和存储器单元之间进行数据传输的方法。 缓存系统具有双向先进先出缓冲区和双向缓存控制器。 双向先入先出缓冲区还具有第一缓存数据区和第二缓存数据区。 第一高速缓存数据区域和第二高速缓存数据区域能够保存一批第一高速缓存数据和一批第二高速缓存数据。 双向缓存控制器从外围设备接收读请求。 根据该读取请求，所请求的数据和所请求数据之后的数据由双向先入先出缓冲器（FIFO）区域保留。 如果外围设备通过将FRAME信号线保持在使能状态继续请求更多的数据，则第一高速缓存数据区域和第二高速缓存数据区域被交替地用于在随后的数据中读取。 可以进行检查以查看存储在双向高速缓存缓冲区内的请求数据是否与存储在存储器单元内的数据相一致或一致。

公开(公告)号：US07136955B2

公开(公告)日：2006-11-14

申请号：US10980624

申请日：2004-11-03

Applicant: Chun-Yuan Su ,  Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai

Inventor： Chun-Yuan Su ,  Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai

IPC: G06F13/00 ,  G06F13/20 ,  G06F13/36

CPC classification number: G06F13/385 ,  G06F2213/0024

Abstract: An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.

Abstract translation: 扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。 扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。 第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。 扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块。

公开(公告)号：US07107373B2

公开(公告)日：2006-09-12

申请号：US10065524

申请日：2002-10-25

Applicant: Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-Kuo Kao

Inventor： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-Kuo Kao

IPC: G06F13/42 ,  G06F5/06

CPC classification number: G06F13/423 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

公开(公告)号：US20050097254A1

公开(公告)日：2005-05-05

申请号：US10980624

申请日：2004-11-03

Applicant: Chun-Yuan Su ,  Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai

Inventor： Chun-Yuan Su ,  Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai

IPC: G06F13/36 ,  G06F13/38

CPC classification number: G06F13/385 ,  G06F2213/0024

Abstract: An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device

Abstract translation: 扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。 扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。 第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。 扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块

公开(公告)号：US06836829B2

公开(公告)日：2004-12-28

申请号：US09853005

申请日：2001-05-09

Applicant: Chau-Chad Tsai ,  Chi-Che Tsai ,  Chen-Ping Yang

Inventor： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chen-Ping Yang

IPC: G06F1200

CPC classification number: G06F13/4243 ,  G06F12/0875 ,  G06F2212/303

Abstract: A peripheral device interface control chip having a cache system therein and a method of synchronization data transmission between the cache system and an external device in a computer system. The cache system and data synchronization method can be applied to the peripheral device interface control chip having a data buffer and a peripheral device interface controller. The data buffer is located inside the control chip for holding data stream read from a memory unit so that data required by the peripheral device is provided. When the data stream is still valid, the data stream is retained. The peripheral device interface controller is installed inside the control chip. The peripheral device interface controller detects if the data stream inside the data buffer includes the data required by the peripheral device and whether the data stream is still valid or not. The peripheral device interface controller also controls the placement of the data stream retrieved from the memory into the data buffer and state transition of the data buffer.

Abstract translation: 一种其中具有缓存系统的外围设备接口控制芯片以及在计算机系统中的高速缓存系统和外部设备之间的同步数据传输的方法。 缓存系统和数据同步方法可以应用于具有数据缓冲器和外围设备接口控制器的外围设备接口控制芯片。 数据缓冲器位于控制芯片内部，用于保持从存储器单元读取的数据流，从而提供外围设备所需的数据。 当数据流仍然有效时，保留数据流。 外围设备接口控制器安装在控制芯片内。 外围设备接口控制器检测数据缓冲器内的数据流是否包括外围设备所需的数据以及数据流是否仍然有效。 外围设备接口控制器还控制从存储器检索的数据流到数据缓冲器和数据缓冲器的状态转换的放置。

公开(公告)号：US06546448B1

公开(公告)日：2003-04-08

申请号：US09440764

申请日：1999-11-16

Applicant: Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Chi-Che Tsai

Inventor： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Chi-Che Tsai

IPC: G06F1314

CPC classification number: G06F13/362

Abstract: Method and apparatus for arbitrating access to a pci bus by a plurality of functions in a multi-function master. The arbitrating method is performed among the multiple functions of a multi-function master. The arbiter includes a rotating inquiry scheduler (RIS) and a heuristic inquiry initiator (HII). The RIS receives the local inquiry signal from the functional circuit and stores it. According to the local inquiry signal, a bus inquiry signal is generated and sent to the HII, and is sent to the PCI bus to request a use of the PCI bus. If the PCI bus responds a delay transaction termination, the HII can repeatedly send the bus inquiry signal to the PCI bus until the PCI bus grants the privilege to use the PCI bus. The HII then informs the RIS, which arranges the functional circuit to transmit data through the PCI bus.

Abstract translation: 用于通过多功能主机中的多个功能来仲裁对pci总线的访问的方法和装置。 在多功能主机的多个功能之间执行仲裁方法。 仲裁器包括旋转查询调度程序（RIS）和启发式查询启动器（HII）。 RIS从功能电路接收本地查询信号并存储。 根据本地查询信号，生成总线查询信号并将其发送到HII，并发送到PCI总线以请求使用PCI总线。 如果PCI总线响应延迟事务终止，则HII可以将总线查询信号重复发送到PCI总线，直到PCI总线授予使用PCI总线的权限。 然后，HII通知RIS，该RIS将功能电路通过PCI总线传输数据。