公开(公告)号：US07051148B2

公开(公告)日：2006-05-23

申请号：US10055558

申请日：2002-01-22

申请人： Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai ,  Wen-Hao Chuang ,  Chun-Yuan Su

发明人： Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai ,  Wen-Hao Chuang ,  Chun-Yuan Su

IPC分类号： G06F13/36 ,  G06F13/42

CPC分类号： G06F13/4059

摘要： A data transmission sequencing method is disclosed. A data read operation from a primary bus to a secondary bus can be executed without having to wait for the complete transfer of write data stored in posted write buffer transferring to the primary bus, as long as the secondary bus is not in use. In the mean time of the primary bus issues a read operation to the secondary bus, the secondary bus can issues write operation to the bridging device when the secondary bus is not in use. Similarly, there is no need to wait for the completion of read operation. With this type of data transmission sequencing mechanism, idle sessions in a conventional transmission sequencing method are eliminated leading to a higher data transmission rate.

公开(公告)号：US07136955B2

公开(公告)日：2006-11-14

申请号：US10980624

申请日：2004-11-03

申请人： Chun-Yuan Su ,  Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai

发明人： Chun-Yuan Su ,  Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai

IPC分类号： G06F13/00 ,  G06F13/20 ,  G06F13/36

CPC分类号： G06F13/385 ,  G06F2213/0024

摘要： An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.

摘要翻译： 扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。 扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。 第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。 扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块。

公开(公告)号：US20050097254A1

公开(公告)日：2005-05-05

申请号：US10980624

申请日：2004-11-03

申请人： Chun-Yuan Su ,  Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai

发明人： Chun-Yuan Su ,  Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai

IPC分类号： G06F13/36 ,  G06F13/38

CPC分类号： G06F13/385 ,  G06F2213/0024

摘要： An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device

摘要翻译： 扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。 扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。 第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。 扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块

公开(公告)号：US06721833B2

公开(公告)日：2004-04-13

申请号：US09735412

申请日：2000-12-12

申请人： Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Chi-Che Tsai

发明人： Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Chi-Che Tsai

IPC分类号： G06F1336

CPC分类号： G06F13/36

摘要： A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second control chips through a bus, the bus comprises a bidirectional bus The first control chip usually control the authority to use the bus, however the second control chip has higher priority to use the bus. Accompany with a bus specification without waiting cycle, to arbitrate the authority to use the bus can be done fast and without errors. Therefore, no GNT signal line is required and the arbitration time reduces.

摘要翻译： 一种控制芯片组内的总线仲裁方法，控制芯片组还包括第一控制芯片和第二控制芯片，数据通过总线在第一和第二控制芯片之间传输，总线包括双向总线第一控制芯片通常 控制使用总线的权限，但第二个控制芯片具有使用总线的优先级。 伴随总线规格无等待周期，仲裁权限使用总线可以快速，毫无错误地完成。 因此，不需要GNT信号线，仲裁时间缩短。

公开(公告)号：US06684284B1

公开(公告)日：2004-01-27

申请号：US09718811

申请日：2000-11-22

申请人： Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Chi-Che Tsai

发明人： Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Chi-Che Tsai

IPC分类号： G06F944

CPC分类号： G06F13/4027

摘要： A data transaction method between control chips. Data buffers of the control chips of the control chipset have fixed size and amount. In addition, read/write acknowledge commands are asserted in sequence according to read/write commands, by which the control chips can detect the status of the buffers within another control chips. When a control chip asserts a command, the corresponding data must be ready in advance. Therefore, the signal line for providing the waiting status, data transaction cycle and stop/retry protocol can be omitted. Accordingly, commands or data can be continuously transmitted without waiting, stop or retry, the performance is improved.

摘要翻译： 控制芯片之间的数据交易方法。 控制芯片组的控制芯片的数据缓冲器具有固定的尺寸和数量。 此外，读/写确认命令根据读/写命令依次被断言，通过该命令，控制芯片可以检测另一个控制芯片内的缓冲器的状态。 当控制芯片发出命令时，相应的数据必须提前准备就绪。 因此，可以省略用于提供等待状态，数据事务周期和停止/重试协议的信号线。 因此，可以连续发送命令或数据，而无需等待，停止或重试，提高性能。

公开(公告)号：US06546448B1

公开(公告)日：2003-04-08

申请号：US09440764

申请日：1999-11-16

申请人： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Chi-Che Tsai

发明人： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Chi-Che Tsai

IPC分类号： G06F1314

CPC分类号： G06F13/362

摘要： Method and apparatus for arbitrating access to a pci bus by a plurality of functions in a multi-function master. The arbitrating method is performed among the multiple functions of a multi-function master. The arbiter includes a rotating inquiry scheduler (RIS) and a heuristic inquiry initiator (HII). The RIS receives the local inquiry signal from the functional circuit and stores it. According to the local inquiry signal, a bus inquiry signal is generated and sent to the HII, and is sent to the PCI bus to request a use of the PCI bus. If the PCI bus responds a delay transaction termination, the HII can repeatedly send the bus inquiry signal to the PCI bus until the PCI bus grants the privilege to use the PCI bus. The HII then informs the RIS, which arranges the functional circuit to transmit data through the PCI bus.

摘要翻译： 用于通过多功能主机中的多个功能来仲裁对pci总线的访问的方法和装置。 在多功能主机的多个功能之间执行仲裁方法。 仲裁器包括旋转查询调度程序（RIS）和启发式查询启动器（HII）。 RIS从功能电路接收本地查询信号并存储。 根据本地查询信号，生成总线查询信号并将其发送到HII，并发送到PCI总线以请求使用PCI总线。 如果PCI总线响应延迟事务终止，则HII可以将总线查询信号重复发送到PCI总线，直到PCI总线授予使用PCI总线的权限。 然后，HII通知RIS，该RIS将功能电路通过PCI总线传输数据。

公开(公告)号：US08060676B2

公开(公告)日：2011-11-15

申请号：US11433195

申请日：2006-05-11

申请人： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-kuo Kao

发明人： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-kuo Kao

IPC分类号： G06F13/42 ,  G06F5/06 ,  G06F13/36

CPC分类号： G06F13/423 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

摘要翻译： 本发明提供了一种在总线上热切换数据传输速率的方法，以热切换控制芯片之间的总线的数据传输速率，而无需复位。 当控制芯片之间的总线需要大量的数据传输时，总线被热切换到更高的数据传输速率，以满足数据传输的要求。 相反，当控制芯片之间的总线需要更少的数据传输量时，总线被热切换到较低的数据传输速率以节省功耗。

公开(公告)号：US06622213B2

公开(公告)日：2003-09-16

申请号：US09881861

申请日：2001-06-15

申请人： Chau-Chad Tsai ,  Chen-Ping Yang ,  Chi-Che Tsai

发明人： Chau-Chad Tsai ,  Chen-Ping Yang ,  Chi-Che Tsai

IPC分类号： G06F1300

CPC分类号： G06F12/0846

摘要： A two-way cache system for interfacing with a peripheral device and a method of operating a two-way cache system for carrying out data transmission between a peripheral device and a memory unit. The cache system has a two-way first-in first-out buffer region and a two-way cache controller. The two-way first-in first-out buffer region further has a first cache data region and a second cache data region. The first cache data region and the second cache data region are capable of holding a batch of first cache data and a batch of second cache data. The two-way cache controller receives a read request from the peripheral device. According to the read request, the requested data and data that ensues or comes after the requested data are retained by the two-way first-in first-out buffer (FIFO) region. If the peripheral device continues to request more data by maintaining a FRAME signal line in an enabled state, the first cache data region and the second cache data region are alternately used to read in subsequent data. A check may be made to see if requested data stored inside the two-way cache buffer region is coherent or consistent with data stored inside the memory unit.

摘要翻译： 一种用于与外围设备进行接口的双向缓存系统和一种操作双向高速缓存系统以在外围设备和存储器单元之间进行数据传输的方法。 缓存系统具有双向先进先出缓冲区和双向缓存控制器。 双向先入先出缓冲区还具有第一缓存数据区和第二缓存数据区。 第一高速缓存数据区域和第二高速缓存数据区域能够保存一批第一高速缓存数据和一批第二高速缓存数据。 双向缓存控制器从外围设备接收读请求。 根据该读取请求，所请求的数据和所请求数据之后的数据由双向先入先出缓冲器（FIFO）区域保留。 如果外围设备通过将FRAME信号线保持在使能状态继续请求更多的数据，则第一高速缓存数据区域和第二高速缓存数据区域被交替地用于在随后的数据中读取。 可以进行检查以查看存储在双向高速缓存缓冲区内的请求数据是否与存储在存储器单元内的数据相一致或一致。

公开(公告)号：US20060206644A1

公开(公告)日：2006-09-14

申请号：US11433195

申请日：2006-05-11

申请人： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-kuo Kao

发明人： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-kuo Kao

IPC分类号： G06F13/42

CPC分类号： G06F13/423 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

公开(公告)号：US06934789B2

公开(公告)日：2005-08-23

申请号：US09894684

申请日：2001-06-27

申请人： Sheng-Chang Peng ,  Chau-Chad Tsai ,  Hsuan-Yi Wang ,  Chi-Che Tsai

发明人： Sheng-Chang Peng ,  Chau-Chad Tsai ,  Hsuan-Yi Wang ,  Chi-Che Tsai

IPC分类号： G06F13/42 ,  G06F13/38

CPC分类号： G06F13/423

摘要： A bus data interface, structure and method for transmitting the data of a PCI bus is disclosed. The bus data interface comprises a high-bit transmitting buffer, a low-bit transmitting buffer, a multiplexer, a strobe generator, and a data distributor. The strobe generator utilizes the bus request signal and bus grant signal to transmit a data strobe signal in response to the PCI clock. According to the rising edge and falling edge of the data strobe signal, the data distributor retrieves data according to the data strobe signal. Further, the invention is compatible with the original PCI bus and allows the PCI bus to transmit data with a dual speed.

摘要翻译： 公开了一种用于发送PCI总线的数据的总线数据接口，结构和方法。 总线数据接口包括高位发送缓冲器，低位发送缓冲器，复用器，选通发生器和数据分配器。 选通发生器利用总线请求信号和总线许可信号来响应于PCI时钟发送数据选通信号。 根据数据选通信号的上升沿和下降沿，数据分配器根据数据选通信号检索数据。 此外，本发明与原始PCI总线兼容，并允许PCI总线以双速传输数据。