公开(公告)号：US08098792B2

公开(公告)日：2012-01-17

申请号：US12790854

申请日：2010-05-31

Applicant: Kuo-Hua Hsu ,  Chun-Hsin Liu ,  Yung-Chih Chen ,  Chih-Ying Lin

Inventor： Kuo-Hua Hsu ,  Chun-Hsin Liu ,  Yung-Chih Chen ,  Chih-Ying Lin

IPC: G11C19/00

CPC classification number: G11C19/184 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2320/043 ,  G11C19/28

Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.

公开(公告)号：US09087596B2

公开(公告)日：2015-07-21

申请号：US13204003

申请日：2011-08-05

Applicant: Kuo-Chang Su ,  Yung-Chih Chen ,  Yu-Chung Yang ,  Chih-Ying Lin

Inventor： Kuo-Chang Su ,  Yung-Chih Chen ,  Yu-Chung Yang ,  Chih-Ying Lin

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G11C19/28 ,  G09G3/3659 ,  G09G3/3677 ,  G09G2300/0447 ,  G09G2330/023

Abstract: The disclosure provides a gate driving circuit on array applied to a display panel with charge sharing pixel structure. In particular, the gate driving circuit is adapted to receive multi-phase clock signal and includes a plurality of shift registers. Each shift register includes a driving circuit including a first driving transistor and a second driving transistor, a pull-down unit and at least one pull-up unit, so that is capable of generating mutually non-overlapped main gate driving signal and sub gate driving signal. Furthermore, the advantage of the disclosure is to provide a gate driving circuit with simplified circuit structure and circuit layout.

Abstract translation: 本公开提供了阵列上施加到电荷共享像素结构的显示面板上的栅极驱动电路。 特别地，栅极驱动电路适于接收多相时钟信号并且包括多个移位寄存器。 每个移位寄存器包括包括第一驱动晶体管和第二驱动晶体管的驱动电路，下拉单元和至少一个上拉单元，使得能够产生相互不重叠的主栅极驱动信号和子栅极驱动 信号。 此外，本公开的优点是提供一种具有简化的电路结构和电路布局的栅极驱动电路。

公开(公告)号：US08515000B2

公开(公告)日：2013-08-20

申请号：US13044773

申请日：2011-03-10

Applicant: Yu-Chung Yang ,  Yung-Chih Chen ,  Chih-Ying Lin ,  Kun-Yueh Lin

Inventor： Yu-Chung Yang ,  Yung-Chih Chen ,  Chih-Ying Lin ,  Kun-Yueh Lin

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/287

Abstract: A shift register circuit includes a plurality of shift registers. Each of the shift registers is configured for outputting a corresponding start-pulse signal and a corresponding driving-pulse signal. Each of the shift registers includes a pull-up circuit, a first driving circuit, a second driving circuit and a discharging circuit. The pull-up circuit is configured for charging a first node. The first driving circuit is configured for generating the corresponding start-pulse signal, and the second driving circuit is configured for generating the corresponding driving-pulse signal. The discharging circuit firstly discharges the first node before discharging an output terminal of the second driving circuit.

Abstract translation: 移位寄存器电路包括多个移位寄存器。 每个移位寄存器被配置为输出相应的起始脉冲信号和相应的驱动脉冲信号。 每个移位寄存器包括上拉电路，第一驱动电路，第二驱动电路和放电电路。 上拉电路被配置为对第一节点进行充电。 第一驱动电路被配置为产生相应的起始脉冲信号，并且第二驱动电路被配置为产生相应的驱动脉冲信号。 在放电第二驱动电路的输出端子之前，放电电路首先对第一节点进行放电。

公开(公告)号：US20120169679A1

公开(公告)日：2012-07-05

申请号：US13316572

申请日：2011-12-12

Applicant: Chih-Ying Lin ,  Chun-Hsin Liu ,  Kuo-Chang Su ,  Yung-Chih Chen

Inventor： Chih-Ying Lin ,  Chun-Hsin Liu ,  Kuo-Chang Su ,  Yung-Chih Chen

IPC: G09G3/36 ,  G06F3/038

CPC classification number: G09G3/3688 ,  G02F1/13624

Abstract: A liquid crystal display device includes a plurality of pixel driving circuits and a pixel array. Each pixel driving circuit of the plurality of pixel driving circuits includes four thin film transistors and has four output terminals, where each thin film transistor is used for driving an output terminal of the four output terminals, and the four output terminals are coupled to two gate lines and two sharing lines respectively for outputting two main output signals and two sharing output signals. The phases and timings of the two main output signals and the two sharing output signals are all the same. A pixel of the pixel array is charged/discharged to a specific voltage level according to a main output signal of the two main output signals, a sharing output signal, and a signal of a data line.

Abstract translation: 液晶显示装置包括多个像素驱动电路和像素阵列。 多个像素驱动电路的每个像素驱动电路包括四个薄膜晶体管，并且具有四个输出端子，其中每个薄膜晶体管用于驱动四个输出端子的输出端子，并且四个输出端子耦合到两个栅极 线路和两条共用线路分别输出两路主输出信号和两路共享输出信号。 两个主输出信号和两个共享输出信号的相位和时序都相同。 像素阵列的像素根据两个主输出信号的主输出信号，共享输出信号和数据线的信号而被充/放电到特定电压电平。

公开(公告)号：US20120032941A1

公开(公告)日：2012-02-09

申请号：US13190446

申请日：2011-07-25

Applicant: Yung-Chih Chen ,  Kuo-Chang Su ,  Chih-Ying Lin ,  Yu-Chung Yang

Inventor： Yung-Chih Chen ,  Kuo-Chang Su ,  Chih-Ying Lin ,  Yu-Chung Yang

IPC: G09G3/36 ,  G09G5/00

CPC classification number: G09G3/3677 ,  G09G2330/021

Abstract: A liquid crystal display device includes a timing controller and a charge-sharing circuit. The timing controller is configured to provide a plurality of input clock signals having duty cycle smaller than ⅓. The charge-sharing circuit is configured to allow charge-sharing to occur between a specific input clock signal and two other input clock signals respectively during the signal rising period and signal falling period of the specific input clock signal, thereby providing a plurality of output clock signals for driving a shift register.

Abstract translation: 液晶显示装置包括定时控制器和电荷共享电路。 定时控制器被配置为提供占空比小于1/3的多个输入时钟信号。 电荷共享电路被配置为在特定输入时钟信号的信号上升周期和信号下降周期期间分别在特定输入时钟信号和两个其它输入时钟信号之间进行电荷共享，从而提供多个输出时钟 用于驱动移位寄存器的信号。

公开(公告)号：US20110216877A1

公开(公告)日：2011-09-08

申请号：US13110948

申请日：2011-05-19

Applicant: Kuo-Hua Hsu ,  Chun-Hsin Liu ,  Yung-Chih Chen ,  Chih-Ying Lin ,  Kuo-Chang Su ,  Yu-Chung Yang

Inventor： Kuo-Hua Hsu ,  Chun-Hsin Liu ,  Yung-Chih Chen ,  Chih-Ying Lin ,  Kuo-Chang Su ,  Yu-Chung Yang

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G2310/0286

Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.

Abstract translation: 具有波形整形功能的移位寄存器电路包括多个移位寄存器级。 每个移位寄存器级包括第一输入单元，上拉单元，下拉电路，第二输入单元，控制单元和波形整形单元。 第一输入单元用于响应于第一门信号输出第一驱动控制电压。 上拉单元响应于第一驱动控制电压拉起第二门信号。 下拉电路用于下拉第一驱动控制电压和第二栅极信号。 第二输入单元用于响应于第一门信号输出第二驱动控制电压。 控制单元响应于第二驱动控制电压和辅助信号提供控制信号。 波形整形单元响应于控制信号对第二门信号执行波形整形操作。

公开(公告)号：US20120219105A1

公开(公告)日：2012-08-30

申请号：US13468047

申请日：2012-05-10

Applicant: Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

Inventor： Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

IPC: G11C19/36 ,  G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract translation: 移位寄存器电路包括用于提供多个门信号的多个移位寄存器级。 每个移位寄存器级包括上拉单元，上拉控制单元，输入单元，第一下拉单元，第二下拉单元和下拉控制单元。 上拉控制单元根据驱动控制电压和第一时钟产生第一控制信号。 上拉单元根据第一控制信号上拉相应的门信号。 输入单元用于根据具有与第一时钟相反的相位的第二时钟输入前一移位寄存器级的门信号以变为驱动控制电压。 下拉控制单元根据驱动控制电压产生第二控制信号。 第一和第二下拉单元根据第二控制信号分别下拉对应的门信号和第一控制信号。

公开(公告)号：US20120153996A1

公开(公告)日：2012-06-21

申请号：US13204003

申请日：2011-08-05

Applicant: Kuo-Chang SU ,  Yung-Chih Chen ,  Yu-Chung Yang ,  Chih-Ying Lin

Inventor： Kuo-Chang SU ,  Yung-Chih Chen ,  Yu-Chung Yang ,  Chih-Ying Lin

IPC: H03K5/00

CPC classification number: G11C19/28 ,  G09G3/3659 ,  G09G3/3677 ,  G09G2300/0447 ,  G09G2330/023

Abstract: The disclosure provides a gate driving circuit on array applied to a display panel with charge sharing pixel structure. In particular, the gate driving circuit is adapted to receive multi-phase clock signal and includes a plurality of shift registers. Each shift register includes a driving circuit including a first driving transistor and a second driving transistor, a pull-down unit and at least one pull-up unit, so that is capable of generating mutually non-overlapped main gate driving signal and sub gate driving signal. Furthermore, the advantage of the disclosure is to provide a gate driving circuit with simplified circuit structure and circuit layout.

Abstract translation: 本公开提供了阵列上施加到电荷共享像素结构的显示面板上的栅极驱动电路。 特别地，栅极驱动电路适于接收多相时钟信号并且包括多个移位寄存器。 每个移位寄存器包括包括第一驱动晶体管和第二驱动晶体管的驱动电路，下拉单元和至少一个上拉单元，使得能够产生相互不重叠的主栅极驱动信号和子栅极驱动 信号。 此外，本公开的优点是提供一种具有简化的电路结构和电路布局的栅极驱动电路。

公开(公告)号：US20120075275A1

公开(公告)日：2012-03-29

申请号：US13049920

申请日：2011-03-17

Applicant: Yung-Chih Chen ,  Kuo-Chang Su ,  Chih-Ying Lin ,  Yu-Chung Yang

Inventor： Yung-Chih Chen ,  Kuo-Chang Su ,  Chih-Ying Lin ,  Yu-Chung Yang

IPC: G09G5/00

CPC classification number: G09G3/3677 ,  G09G2300/0447 ,  G09G2310/0262 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2320/0242

Abstract: A display device having bi-directional shift registers is disclosed. The display device includes a display panel, a first dummy shift register set, a second dummy shift register set, a third dummy shift register sets, a fourth dummy shift register sets, a first valid shift register set coupled between the first dummy shift register set and the second dummy shift register set, a second valid shift register set coupled between the third dummy shift register set and the fourth dummy shift register set, and a first directional circuit coupled to a first valid register in the first valid register set and the third dummy shift register set.

Abstract translation: 公开了一种具有双向移位寄存器的显示装置。 显示装置包括显示面板，第一虚拟移位寄存器组，第二虚拟移位寄存器组，第三虚拟移位寄存器组，第四虚拟移位寄存器组，第一有效移位寄存器组，耦合在第一虚拟移位寄存器组 和第二虚拟移位寄存器组，耦合在第三虚拟移位寄存器组和第四虚拟移位寄存器组之间的第二有效移位寄存器组，以及耦合到第一有效寄存器集合中的第一有效寄存器的第一定向电路， 虚拟移位寄存器组。

公开(公告)号：US20110142192A1

公开(公告)日：2011-06-16

申请号：US12959378

申请日：2010-12-03

Applicant: Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

Inventor： Chih-Ying Lin ,  Kun-Yueh Lin ,  Yu-Chung Yang ,  Kuo-Hua Hsu

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract translation: 移位寄存器电路包括用于提供多个门信号的多个移位寄存器级。 每个移位寄存器级包括上拉单元，上拉控制单元，输入单元，第一下拉单元，第二下拉单元和下拉控制单元。 上拉控制单元根据驱动控制电压和第一时钟产生第一控制信号。 上拉单元根据第一控制信号上拉相应的门信号。 输入单元用于根据具有与第一时钟相反的相位的第二时钟输入前一移位寄存器级的门信号以变为驱动控制电压。 下拉控制单元根据驱动控制电压产生第二控制信号。 第一和第二下拉单元根据第二控制信号分别下拉对应的门信号和第一控制信号。