公开(公告)号：US20080191834A1

公开(公告)日：2008-08-14

申请号：US11704987

申请日：2007-02-12

Applicant: Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Xing-Guang Huang ,  Wei-Cheng Lien

Inventor： Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Xing-Guang Huang ,  Wei-Cheng Lien

IPC: H01C7/12 ,  C03C11/00

CPC classification number: H01C7/105 ,  B82Y30/00 ,  C03C14/006 ,  C03C2214/05 ,  C03C2214/08 ,  C03C2214/16 ,  C04B35/453 ,  C04B35/46 ,  C04B35/4682 ,  C04B35/47 ,  C04B35/565 ,  C04B35/624 ,  C04B35/62805 ,  C04B35/62807 ,  C04B35/62886 ,  C04B2235/3275 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/36 ,  C04B2235/405 ,  C04B2235/408 ,  C04B2235/5436 ,  C04B2235/5445 ,  C04B2235/5454 ,  C04B2235/6025 ,  H01C7/12

Abstract: A low-capacitance multilayer chip varistor has capacitance lower than 0.5 pF at 1 MHz and has a characteristic of resisting more than thousands of times of 8 KV electrostatic shock, which comprises a ceramic main body, outer electrodes disposed at two ends of the ceramic main body and inner electrodes disposed therein; the ceramic main body comprises inorganic glass of 3˜50 wt % and semi-conductive or conductive particles of 50˜97 wt % with particle size of more than 0.1 μm, and a layer of inorganic glass film covers the surface of semi-conductive or conductive particles, wherein the inorganic glass film contains semi-conductive or conductive particles of submicron or nanometer which is smaller than 1 micron, and the quantity contained of semi-conductive or conductive particles is less than 20 wt % of that of inorganic glass.

Abstract translation: 低容量多层片式压敏电阻在1MHz时的电容低于0.5pF，具有耐8千伏静电电击的数千倍的特性，其中包括一陶瓷主体，外电极位于陶瓷主体的两端 主体和内部电极; 陶瓷主体包括3〜50重量％的无机玻璃和50〜97重量％的粒径大于0.1微米的半导体或导电颗粒，无机玻璃膜层覆盖半导体或 导电颗粒，其中无机玻璃膜含有小于1微米的亚微米或纳米的半导电或导电颗粒，并且半导体或导电颗粒所含的量小于无机玻璃的20重量％。

公开(公告)号：US08363382B2

公开(公告)日：2013-01-29

申请号：US13024470

申请日：2011-02-10

Applicant: Ching-Hohn Lien ,  Hong-Zong Xu

Inventor： Ching-Hohn Lien ,  Hong-Zong Xu

IPC: H01G4/005

CPC classification number: H01G4/005 ,  H01G4/30 ,  Y10T428/12056

Abstract: A multilayer ceramic device comprises a laminated ceramic body having opposite end surfaces, a pair of conductive electrodes each respectively attached to one end surface of the laminated ceramic body and a plurality of alternately staggered internal electrodes within the laminated ceramic body configured in an alternating manner and each electrically connected to the corresponding conductive electrodes respectively; each conductive electrodes of the multilayer ceramic device is further covered with a solder paste layer so that the multilayer ceramic device is thus made without any plating step and no need of treating waste liquid nickel or waste liquid tin as well as no problem of environmental pollution caused by plating solution, thereby lowering manufacturing costs and reducing processing time.

Abstract translation: 多层陶瓷器件包括具有相对端面的层叠陶瓷体，分别安装在层叠陶瓷体的一个端面上的一对导电电极和层叠陶瓷体内的多个交错交错的内部电极，其以交替的方式配置和 各自电连接到相应的导电电极; 多层陶瓷器件的每个导电电极进一步用焊膏层覆盖，使得多层陶瓷器件因此不经任何电镀步骤而制成，并且不需要处理废液镍或废液锡，并且没有引起环境污染的问题 通过电镀液，降低制造成本，缩短加工时间。

公开(公告)号：US20120135563A1

公开(公告)日：2012-05-31

申请号：US13298458

申请日：2011-11-17

Applicant: Ching-Hohn LIEN ,  Jie-An ZHU

Inventor： Ching-Hohn LIEN ,  Jie-An ZHU

IPC: H01L21/02

CPC classification number: H01C7/112 ,  H01C7/18

Abstract: A low-temperature firing process is available for cost saving to produce a multilayer chip ZnO varistor containing pure silver (Ag) formed as internal electrodes and calcined at ultralow firing temperature of 850-900° C., which process comprises: a) individually preparing ZnO grains in advance doped with doping ions for promotion of semi-conductivity of ZnO grains if calcined; b) individually preparing a desired high-impedance sintering material to be fired as grain boundaries to encapsulate ZnO grains; c) mixing the doped ZnO grains of Step a) with the high-impedance sintering material of Step b) in a predetermined ratio to form a mixture and proceeding with an initial sintering to have the mixture sintered and ground as composite ZnO ceramic powders, and d) processing the sintered mixture of Step c) to make multilayer chip ZnO varistors containing pure silver (Ag) internal electrodes but sintered at ultralow firing temperature of 850-900° C.

Abstract translation: 低成本焙烧工艺可以节约成本，生产出一种含有形成内部电极的纯银（Ag）的多层芯片ZnO压敏电阻，并在850-900℃的超低烧结温度下煅烧，该方法包括：a）单独制备 预先掺杂掺杂离子的ZnO晶粒，如果煅烧，则促进ZnO晶粒的半导电性; b）单独制备待烧结的期望的高阻抗烧结材料作为晶界以包封ZnO颗粒; c）将步骤a）的掺杂ZnO晶粒与步骤b）的高阻抗烧结材料以预定比例混合，形成混合物，并进行初始烧结，将混合物烧结并研磨为复合ZnO陶瓷粉末; d）加工步骤c）的烧结混合物以制备含有纯银（Ag）内部电极但在850-900℃的超低烧结温度下烧结的多层片状ZnO压敏电阻