公开(公告)号：US07206930B2

公开(公告)日：2007-04-17

申请号：US11002258

申请日：2004-12-03

Applicant: Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

Inventor： Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

IPC: G06F9/24

CPC classification number: G06F13/4004 ,  G06F13/423 ,  G06F2213/0024

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state. Subsequently, the configuration value fetched from the non-volatile memory is asserted to the at least one configurable device to configure the configurable device, and then the processor reset signal is deasserted, and the at least one configurable device is thereby completely configured.

Abstract translation: 提供了一种减少具有至少一个可配置设备的计算机系统中的捆扎设备的方法，其包括以下步骤。 首先提供存储在非易失性存储器中的配置值。 在计算机系统的上电和复位期间，高速外设总线的处理器复位信号和总线复位信号都被断言，其中高速外设总线被包括在计算机系统中。 当高速外设总线的工作时钟达到其工作电压和频率时，从非易失性存储器中取出配置值。 取出步骤被重复，直到获取的配置值的最高有效位（MSB）从第一状态改变到第二状态。 随后，从非易失性存储器取出的配置值被断言给至少一个可配置设备以配置可配置设备，然后解除处理器复位信号，并且由此完全配置至少一个可配置设备。

公开(公告)号：US20060250720A1

公开(公告)日：2006-11-09

申请号：US11381403

申请日：2006-05-03

Applicant: Chang-Wei Hsu ,  Chun-Chieh Wu

Inventor： Chang-Wei Hsu ,  Chun-Chieh Wu

IPC: G11B5/09

CPC classification number: G11C29/883 ,  G11C29/765 ,  G11C29/88

Abstract: A portable data storage device includes a first storage unit having a data storing zone and a reserved zone for bad blocks in the first storage unit, and a second storage unit having a look-up table. The look-up table lists a number of configuration modes for the portable data storage device, each defining specific allocation sizes for the reserved zone and the data storing zone. The portable data storage device is configured to use a kth configuration mode. A method for dynamic memory management includes: i) determining a number of the bad blocks assigned to the reserved zone; ii) with reference to the look-up table, determining if this number is greater than a limit associated with the kth configuration mode; and iii) if so, reconfiguring the portable data storage device to use a (k+1)th configuration mode.

Abstract translation: 便携式数据存储装置包括具有第一存储单元中的坏块的数据存储区和预留区的第一存储单元和具有查找表的第二存储单元。 查找表列出了便携式数据存储设备的多个配置模式，每个配置模式定义了保留区域和数据存储区域的特定分配大小。 便携式数据存储装置被配置为使用第k种配置模式。 一种用于动态存储器管理的方法包括：i）确定分配给保留区的坏块的数量; ii）参考查找表，确定该数量是否大于与第k个配置模式相关联的限制; 以及iii）如果是，则将便携式数据存储装置重新配置为使用第（k + 1）配置模式。

公开(公告)号：US07521330B2

公开(公告)日：2009-04-21

申请号：US11757763

申请日：2007-06-04

Applicant: Chun Chieh Wu ,  Chi-Feng Huang ,  Chun-Hung Chen ,  Chih-Ping Chao ,  John Chern

Inventor： Chun Chieh Wu ,  Chi-Feng Huang ,  Chun-Hung Chen ,  Chih-Ping Chao ,  John Chern

IPC: H01L21/20

CPC classification number: H01L27/0629 ,  H01L29/7833

Abstract: A method for forming a capacitor includes forming a dielectric layer over a substrate. A conductive layer is formed over the dielectric layer. Dopants are implanted through at least one of the dielectric layer and the conductive layer after forming the dielectric layer so as to form a conductive region under the dielectric layer, wherein the conductive layer is a top electrode of the capacitor and the conductive region is a bottom electrode of the capacitor.

Abstract translation: 形成电容器的方法包括在衬底上形成电介质层。 在电介质层上形成导电层。 在形成电介质层之后，通过介电层和导电层中的至少一个注入掺杂剂，以在电介质层下方形成导电区域，其中导电层是电容器的顶部电极，导电区域是底部 电容器的电极。

公开(公告)号：US07436667B2

公开(公告)日：2008-10-14

申请号：US11545419

申请日：2006-10-11

Applicant: Chun-Chieh Wu ,  Hung-Chun Chu ,  Hsi-Feng Lin

Inventor： Chun-Chieh Wu ,  Hung-Chun Chu ,  Hsi-Feng Lin

IPC: H05K7/20 ,  F28F7/00

CPC classification number: G06F1/20 ,  H01L23/467 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device has a first circuit board, a first fan, a second circuit board, a first heat sink, and a first air ventilation duct. The first fan and the first circuit board are electrically connected together. The second circuit board is electrically connected to the first circuit board; the first heat sink is electrically connected to the second circuit board; and the first air ventilation duct is connected to the first fan and the first heat sink. The first heat sink introduce the heat generated by the electronic element on the second circuit board to the first fan for better cooling performance. Therefore, the present invention requires only the first fan and the second fan, but is able to provide high cooling efficiencies with a low noise signature.

Abstract translation: 电子设备具有第一电路板，第一风扇，第二电路板，第一散热器和第一空气通风导管。 第一风扇和第一电路板电连接在一起。 第二电路板电连接到第一电路板; 第一散热器电连接到第二电路板; 并且第一通风管道连接到第一风扇和第一散热器。 第一散热器将第二电路板上的电子元件产生的热量引入第一风扇以获得更好的冷却性能。 因此，本发明仅需要第一风扇和第二风扇，但是能够以低噪声特征提供高冷却效率。

公开(公告)号：US20130096018A1

公开(公告)日：2013-04-18

申请号：US13426485

申请日：2012-03-21

Applicant: Ming-Tsang Wu ,  Deng-Chyang Wu ,  Hung-Ju Su ,  Chah-Hwa Chou ,  Jie-Len Huang ,  Yu-Kuei Chen ,  Chun-Chieh Wu

Inventor： Ming-Tsang Wu ,  Deng-Chyang Wu ,  Hung-Ju Su ,  Chah-Hwa Chou ,  Jie-Len Huang ,  Yu-Kuei Chen ,  Chun-Chieh Wu

IPC: G01N21/64 ,  G01N33/574 ,  C07H21/04 ,  C40B30/04

CPC classification number: C12Q1/6886 ,  C12Q2600/118 ,  C12Q2600/158 ,  G01N33/57407 ,  G01N2333/70596

Abstract: The present invention provides a method for predicting the survival rate and prognosis of esophageal carcinoma patients, which is characterized in examining the expression level of a specific gene, peptidase inhibitor 3 (PI3) or CD14 antigen (CD14) in a sample, and comparing to the average expression level of said specific gene from patients to determine the survival and prognosis status for esophageal cancer. The present invention further provides a kit for predicting the survival rate and prognosis of esophageal carcinoma patients.

Abstract translation: 本发明提供一种预测食管癌患者的存活率和预后的方法，其特征在于检查样品中特异性基因，肽酶抑制剂3（PI3）或CD14抗原（CD14）的表达水平，并比较 所述特定基因的平均表达水平来自患者，以确定食管癌的存活和预后状态。 本发明还提供了一种用于预测食管癌患者的存活率和预后的试剂盒。

公开(公告)号：US06845444B2

公开(公告)日：2005-01-18

申请号：US09934574

申请日：2001-08-23

Applicant: Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

Inventor： Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

IPC: G06F3/00 ,  G06F9/24 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4004 ,  G06F13/423 ,  G06F2213/0024

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state. Subsequently, the configuration value fetched from the non-volatile memory is asserted to the at least one configurable device to configure the configurable device, and then the processor reset signal is deasserted, and the at least one configurable device is thereby completely configured.

Abstract translation: 提供了一种减少具有至少一个可配置设备的计算机系统中的捆扎设备的方法，其包括以下步骤。 首先提供存储在非易失性存储器中的配置值。 在计算机系统的上电和复位期间，高速外设总线的处理器复位信号和总线复位信号都被断言，其中高速外设总线被包括在计算机系统中。 当高速外设总线的工作时钟达到其工作电压和频率时，从非易失性存储器中取出配置值。 取出步骤被重复，直到获取的配置值的最高有效位（MSB）从第一状态改变到第二状态。 随后，从非易失性存储器取出的配置值被断言给至少一个可配置设备以配置可配置设备，然后解除处理器复位信号，并且由此完全配置至少一个可配置设备。

公开(公告)号：US06317813B1

公开(公告)日：2001-11-13

申请号：US09314245

申请日：1999-05-18

Applicant: Jen-Pin Su ,  Chun-Chieh Wu ,  Wen-Hsiang Lin ,  Tsan-hui Chen

Inventor： Jen-Pin Su ,  Chun-Chieh Wu ,  Wen-Hsiang Lin ,  Tsan-hui Chen

IPC: G06F1200

CPC classification number: G06F13/18

Abstract: In a memory controller system, a method for granting a system memory by a memory request arbitrator to a request among a plurality of pending memory access requests is provided. The plurality of the memory access requests includes Rfrsh_Hreq, Crt_Hreq, Group AB, Crt_Lreq and Rfrsh_Lreq and are respectively asserted by a host control circuitry and/or a graphical control circuitry which are implemented and integrated on a single monolithic semiconductor chip. The host control circuitry and the graphical control circuitry shares the system memory and the memory request arbitrator includes a refresh queue and the graphics control circuitry includes a CRT FIFO. The method prioritizes the plurality of the memory access requests in order of Rfrsh_Hreq>Crt_Hreq>Group AB>Crt_Lreq>Rfrsh_Lreq. The Rfsh_Hreq is memory refresh request signal of first type whenever the refresh queue being full, the Crt_Hreq is memory access signal of a first type for fueling the CRT FIFO with display data, the Group AB are memory access request signals of a second type output either from the graphical control circuitry or the host control circuitry, the Crt_Lreq is memory access signal of a third type for fueling the CRT FIFO with display data, the Rfrsh_Lreq is memory refresh request signal of second type whenever the refresh queue being non-empty.

Abstract translation: 在存储器控制器系统中，提供了一种通过存储器请求仲裁器将系统存储器授予多个未决存储器访问请求中的请求的方法。 多个存储器访问请求包括Rfrsh_Hreq，Crt_Hreq，组AB，Crt_Lreq和Rfrsh_Lreq，并且分别由实现并集成在单个单片半导体芯片上的主机控制电路和/或图形控制电路断言。 主机控制电路和图形控制电路共享系统存储器，并且存储器请求仲裁器包括刷新队列，并且图形控制电路包括CRT FIFO。 该方法按照Rfrsh_Hreq> Crt_Hreq> Group AB> Crt_Lreq> Rfrsh_Lreq的顺序对多个存储器访问请求进行优先级排序。 Rfsh_Hreq是刷新队列满时的第一种类型的存储器刷新请求信号，Crt_Hreq是用于向显示数据供给CRT FIFO的第一种存储器访问信号，组AB是第二类型输出的存储器访问请求信号 从图形控制电路或主机控制电路，Crt_Lreq是用于向CRT FIFO加载显示数据的第三种存储器访问信号，每当刷新队列不为空时，Rfrsh_Lreq是第二类型的存储器刷新请求信号。

公开(公告)号：US08169229B2

公开(公告)日：2012-05-01

申请号：US12875151

申请日：2010-09-03

Applicant: Chih-Chang Wang ,  Chih-Ming Chang ,  Chun-Chieh Wu

Inventor： Chih-Chang Wang ,  Chih-Ming Chang ,  Chun-Chieh Wu

IPC: G01R31/26

CPC classification number: G09G3/006 ,  G09G3/3648 ,  G09G2330/12

Abstract: An active device array includes a plurality of scan lines, a plurality of data lines, a plurality of pixel structures, a first testing circuit, a second testing circuit, a third testing circuit and a fourth testing circuit. Each of the pixel structures is connected to one of the scan lines and one of the data lines. The first testing circuit is electrically connected to the odd scan lines; the second testing circuit is electrically connected to the (4n+1)th scan lines wherein n is zero or a positive integer; the third testing circuit is electrically connected to the even scan lines; the fourth testing circuit is electrically connected to the (4n+2)th scan lines.

Abstract translation: 有源器件阵列包括多条扫描线，多条数据线，多个像素结构，第一测试电路，第二测试电路，第三测试电路和第四测试电路。 每个像素结构连接到扫描线之一和数据线之一。 第一测试电路电连接到奇数扫描线; 第二测试电路电连接到其中n为零或正整数的第（4n + 1）扫描线; 第三测试电路电连接到偶数扫描线; 第四测试电路电连接到第（4n + 2）扫描线。

公开(公告)号：US08018543B2

公开(公告)日：2011-09-13

申请号：US12485203

申请日：2009-06-16

Applicant: Chun-Kang Huang ,  Chun-Chieh Wu ,  Chia-Li Su

Inventor： Chun-Kang Huang ,  Chun-Chieh Wu ,  Chia-Li Su

IPC: G02F1/1333 ,  G02F1/1339

CPC classification number: G02F1/13452 ,  G02F2202/22

Abstract: A liquid crystal display (LCD) panel including a first substrate, a second substrate, a liquid crystal layer, a sealant and an electrostatic protection structure is provided. The first substrate and the second substrate are disposed in parallel. The sealant is for sealing the liquid crystal layer between the first substrate and the second substrate. The electrostatic protection structure is disposed within a non-display area outside the sealant. The electrostatic protection structure includes a first line disposed on the first substrate and surrounding the edge of the first substrate.

Abstract translation: 提供了包括第一基板，第二基板，液晶层，密封剂和静电保护结构的液晶显示器（LCD）面板。 第一基板和第二基板平行设置。 密封剂用于密封第一基板和第二基板之间的液晶层。 静电保护结构设置在密封剂外部的非显示区域内。 静电保护结构包括设置在第一基板上并围绕第一基板的边缘的第一线。

公开(公告)号：US20110057680A1

公开(公告)日：2011-03-10

申请号：US12875151

申请日：2010-09-03

Applicant: Chih-Chang Wang ,  Chih-Ming Chang ,  Chun-Chieh Wu

Inventor： Chih-Chang Wang ,  Chih-Ming Chang ,  Chun-Chieh Wu

IPC: G01R31/26

CPC classification number: G09G3/006 ,  G09G3/3648 ,  G09G2330/12

Abstract: An active device array includes a plurality of scan lines, a plurality of data lines, a plurality of pixel structures, a first testing circuit, a second testing circuit, a third testing circuit and a fourth testing circuit. Each of the pixel structures is connected to one of the scan lines and one of the data lines. The first testing circuit is electrically connected to the odd scan lines; the second testing circuit is electrically connected to the (4n+1)th scan lines wherein n is zero or a positive integer; the third testing circuit is electrically connected to the even scan lines; the fourth testing circuit is electrically connected to the (4n+2)th scan lines.

Abstract translation: 有源器件阵列包括多条扫描线，多条数据线，多个像素结构，第一测试电路，第二测试电路，第三测试电路和第四测试电路。 每个像素结构连接到扫描线之一和数据线之一。 第一测试电路电连接到奇数扫描线; 第二测试电路电连接到其中n为零或正整数的第（4n + 1）扫描线; 第三测试电路电连接到偶数扫描线; 第四测试电路电连接到第（4n + 2）扫描线。