公开(公告)号：US07206930B2

公开(公告)日：2007-04-17

申请号：US11002258

申请日：2004-12-03

Applicant: Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

Inventor： Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

IPC: G06F9/24

CPC classification number: G06F13/4004 ,  G06F13/423 ,  G06F2213/0024

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state. Subsequently, the configuration value fetched from the non-volatile memory is asserted to the at least one configurable device to configure the configurable device, and then the processor reset signal is deasserted, and the at least one configurable device is thereby completely configured.

Abstract translation: 提供了一种减少具有至少一个可配置设备的计算机系统中的捆扎设备的方法，其包括以下步骤。 首先提供存储在非易失性存储器中的配置值。 在计算机系统的上电和复位期间，高速外设总线的处理器复位信号和总线复位信号都被断言，其中高速外设总线被包括在计算机系统中。 当高速外设总线的工作时钟达到其工作电压和频率时，从非易失性存储器中取出配置值。 取出步骤被重复，直到获取的配置值的最高有效位（MSB）从第一状态改变到第二状态。 随后，从非易失性存储器取出的配置值被断言给至少一个可配置设备以配置可配置设备，然后解除处理器复位信号，并且由此完全配置至少一个可配置设备。

公开(公告)号：US06862673B2

公开(公告)日：2005-03-01

申请号：US10003168

申请日：2001-11-14

Applicant: Shao-Kuang Lee ,  Jen-Pin Su ,  Tsan-Hui Chen

Inventor： Shao-Kuang Lee ,  Jen-Pin Su ,  Tsan-Hui Chen

IPC: G06F5/10 ,  G06F5/12 ,  G06F12/00

CPC classification number: G06F5/12 ,  G06F2205/123

Abstract: A mechanism for maintaining the first-in first-out order of commands in a multiple-input and multiple-output buffer structure includes a command number generator for generating and assigning a command number to each command entering the buffer structure, and a command number comparator for comparing the command number of the outgoing command at each buffer in the buffer structure to determine which command should exit. Both command number generator and command comparator have a cyclic counter that has a period greater than or equal to the total number of allowable buffer entries in the buffer structure. For maintaining order of posted and non-posted command queues, a pending posted write counter is used in the posted command queue to record the number of pending posted write command and each entry in the non-posted command queue is associated with a dependency counter.

Abstract translation: 用于在多输入和多输出缓冲器结构中维持先进先出命令的机制包括：命令编号发生器，用于产生和分配命令号到进入缓冲器结构的每个命令，命令编号比较器 用于比较缓冲结构中每个缓冲区的输出命令的命令编号，以确定哪个命令应该退出。 命令编号发生器和命令比较器都具有循环计数器，其周期大于或等于缓冲器结构中允许的缓冲器条目的总数。 为了维护发布和未发布的命令队列的顺序，在发布的命令队列中使用挂起的写入计数器来记录挂起的写入命令的数量，并且非发布的命令队列中的每个条目与依赖关系计数器相关联。

公开(公告)号：US06845444B2

公开(公告)日：2005-01-18

申请号：US09934574

申请日：2001-08-23

Applicant: Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

Inventor： Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

IPC: G06F3/00 ,  G06F9/24 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4004 ,  G06F13/423 ,  G06F2213/0024

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state. Subsequently, the configuration value fetched from the non-volatile memory is asserted to the at least one configurable device to configure the configurable device, and then the processor reset signal is deasserted, and the at least one configurable device is thereby completely configured.

Abstract translation: 提供了一种减少具有至少一个可配置设备的计算机系统中的捆扎设备的方法，其包括以下步骤。 首先提供存储在非易失性存储器中的配置值。 在计算机系统的上电和复位期间，高速外设总线的处理器复位信号和总线复位信号都被断言，其中高速外设总线被包括在计算机系统中。 当高速外设总线的工作时钟达到其工作电压和频率时，从非易失性存储器中取出配置值。 取出步骤被重复，直到获取的配置值的最高有效位（MSB）从第一状态改变到第二状态。 随后，从非易失性存储器取出的配置值被断言给至少一个可配置设备以配置可配置设备，然后解除处理器复位信号，并且由此完全配置至少一个可配置设备。

公开(公告)号：US06317813B1

公开(公告)日：2001-11-13

申请号：US09314245

申请日：1999-05-18

Applicant: Jen-Pin Su ,  Chun-Chieh Wu ,  Wen-Hsiang Lin ,  Tsan-hui Chen

Inventor： Jen-Pin Su ,  Chun-Chieh Wu ,  Wen-Hsiang Lin ,  Tsan-hui Chen

IPC: G06F1200

CPC classification number: G06F13/18

Abstract: In a memory controller system, a method for granting a system memory by a memory request arbitrator to a request among a plurality of pending memory access requests is provided. The plurality of the memory access requests includes Rfrsh_Hreq, Crt_Hreq, Group AB, Crt_Lreq and Rfrsh_Lreq and are respectively asserted by a host control circuitry and/or a graphical control circuitry which are implemented and integrated on a single monolithic semiconductor chip. The host control circuitry and the graphical control circuitry shares the system memory and the memory request arbitrator includes a refresh queue and the graphics control circuitry includes a CRT FIFO. The method prioritizes the plurality of the memory access requests in order of Rfrsh_Hreq>Crt_Hreq>Group AB>Crt_Lreq>Rfrsh_Lreq. The Rfsh_Hreq is memory refresh request signal of first type whenever the refresh queue being full, the Crt_Hreq is memory access signal of a first type for fueling the CRT FIFO with display data, the Group AB are memory access request signals of a second type output either from the graphical control circuitry or the host control circuitry, the Crt_Lreq is memory access signal of a third type for fueling the CRT FIFO with display data, the Rfrsh_Lreq is memory refresh request signal of second type whenever the refresh queue being non-empty.

Abstract translation: 在存储器控制器系统中，提供了一种通过存储器请求仲裁器将系统存储器授予多个未决存储器访问请求中的请求的方法。 多个存储器访问请求包括Rfrsh_Hreq，Crt_Hreq，组AB，Crt_Lreq和Rfrsh_Lreq，并且分别由实现并集成在单个单片半导体芯片上的主机控制电路和/或图形控制电路断言。 主机控制电路和图形控制电路共享系统存储器，并且存储器请求仲裁器包括刷新队列，并且图形控制电路包括CRT FIFO。 该方法按照Rfrsh_Hreq> Crt_Hreq> Group AB> Crt_Lreq> Rfrsh_Lreq的顺序对多个存储器访问请求进行优先级排序。 Rfsh_Hreq是刷新队列满时的第一种类型的存储器刷新请求信号，Crt_Hreq是用于向显示数据供给CRT FIFO的第一种存储器访问信号，组AB是第二类型输出的存储器访问请求信号 从图形控制电路或主机控制电路，Crt_Lreq是用于向CRT FIFO加载显示数据的第三种存储器访问信号，每当刷新队列不为空时，Rfrsh_Lreq是第二类型的存储器刷新请求信号。

公开(公告)号：US08593902B2

公开(公告)日：2013-11-26

申请号：US13311352

申请日：2011-12-05

Applicant: Chih-Hsin Lin ,  Tsung-Huang Chen ,  Bing-Shiun Wang ,  Jen-Pin Su

Inventor： Chih-Hsin Lin ,  Tsung-Huang Chen ,  Bing-Shiun Wang ,  Jen-Pin Su

IPC: G11C8/16 ,  G11C7/10

CPC classification number: G11C7/1072 ,  G11C7/1045 ,  G11C7/1066

Abstract: A controller for a DDR PSRAM is provided. The controller includes a single rate processing unit, a double rate processing unit and a selector. The signal rate processing unit obtains a single data rate data according to a first data and a first clock. The double rate processing unit obtains a double data rate data according to a second data and a second clock that is two times the frequency of the first clock. The selector selectively provides any of the single data rate data and the double data rate data to the DDR PSRAM via a common bus according to a control signal.

Abstract translation: 提供了一个用于DDR PSRAM的控制器。 控制器包括单速率处理单元，双速率处理单元和选择器。 信号速率处理单元根据第一数据和第一时钟获得单个数据速率数据。 双速率处理单元根据第二数据和第二时钟的二倍于第一时钟的频率获得双倍数据速率数据。 选择器根据控制信号通过公共总线选择性地将任何单个数据速率数据和双倍数据速率数据提供给DDR PSRAM。

公开(公告)号：US20130058174A1

公开(公告)日：2013-03-07

申请号：US13311352

申请日：2011-12-05

Applicant: Chih-Hsin LIN ,  Tsung-Huang CHEN ,  Bing-Shiun WANG ,  Jen-Pin SU

Inventor： Chih-Hsin LIN ,  Tsung-Huang CHEN ,  Bing-Shiun WANG ,  Jen-Pin SU

IPC: G11C8/18

CPC classification number: G11C7/1072 ,  G11C7/1045 ,  G11C7/1066

Abstract: A controller for a DDR PSRAM is provided. The controller includes a single rate processing unit, a double rate processing unit and a selector. The signal rate processing unit obtains a single data rate data according to a first data and a first clock. The double rate processing unit obtains a double data rate data according to a second data and a second clock that is two times the frequency of the first clock. The selector selectively provides any of the single data rate data and the double data rate data to the DDR PSRAM via a common bus according to a control signal.

Abstract translation: 提供了一个用于DDR PSRAM的控制器。 控制器包括单速率处理单元，双速率处理单元和选择器。 信号速率处理单元根据第一数据和第一时钟获得单个数据速率数据。 双速率处理单元根据第二数据和第二时钟的二倍于第一时钟的频率获得双倍数据速率数据。 选择器根据控制信号通过公共总线选择性地将任何单个数据速率数据和双倍数据速率数据提供给DDR PSRAM。

公开(公告)号：US20070266263A1

公开(公告)日：2007-11-15

申请号：US11432783

申请日：2006-05-11

Applicant: Ming-hsien Lee ,  Jen-pin Su ,  Tsan-hwi Chen

Inventor： Ming-hsien Lee ,  Jen-pin Su ,  Tsan-hwi Chen

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  Y02D10/126

Abstract: The present invention discloses a speed adjustment system and method for performing the same, which is capable to provide different power saving behaviors adaptive for different applications (e.g. a mobile or a normal configuration) and/or different-corner-process chips. The speed adjustment system includes a reference speed generator for pre-storing multiple reference speed value, an operating speed generator for pre-storing multiple operating speed value, a comparing unit for determining whether a predefined logical operational relationship is satisfied with the operating speed value and reference speed value, a voltage controller based on said determination result to vary the operating voltage, and a speed detector for detecting the operating speed value.

Abstract translation: 本发明公开了一种速度调节系统及其执行方法，其能够为不同应用（例如，移动或正常配置）和/或不同角落处理芯片提供不同的省电行为。 速度调节系统包括用于预存储多个参考速度值的参考速度发生器，用于预存储多个操作速度值的操作速度发生器，用于确定预定逻辑操作关系是否满足操作速度值的比较单元，以及 参考速度值，基于所述确定结果以改变操作电压的电压控制器，以及用于检测操作速度值的速度检测器。

公开(公告)号：US20050080938A1

公开(公告)日：2005-04-14

申请号：US11002258

申请日：2004-12-03

Applicant: Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

Inventor： Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

IPC: G06F3/00 ,  G06F9/24 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4004 ,  G06F13/423 ,  G06F2213/0024

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state. Subsequently, the configuration value fetched from the non-volatile memory is asserted to the at least one configurable device to configure the configurable device, and then the processor reset signal is deasserted, and the at least one configurable device is thereby completely configured.

公开(公告)号：US06424189B1

公开(公告)日：2002-07-23

申请号：US09687418

申请日：2000-10-13

Applicant: Jen-Pin Su ,  Tsan-Hui Chen ,  Wen-Hsiang Lin ,  Chun-Chieh Wu ,  Chang-Fu Lin

Inventor： Jen-Pin Su ,  Tsan-Hui Chen ,  Wen-Hsiang Lin ,  Chun-Chieh Wu ,  Chang-Fu Lin

IPC: H03L700

CPC classification number: G06F5/06 ,  H04L7/005 ,  H04L7/02

Abstract: The present invention discloses an apparatus and system for multi-stage event synchronization, whose main object is to eliminate the drawbacks of an expensive synchronization circuit used to balance the data transmissions between an origination agent and a destination agent operating at different frequencies or clock phases as in prior art. The apparatus of the present invention organizes the slower one with multi-stage chains, each of which comprises a simple synchronization circuit and an XOR gate, for receiving the number of events transmitted from the faster one. Therefore, the slower one will not miss the data from the faster one.

Abstract translation: 本发明公开了一种用于多级事件同步的装置和系统，其主要目的是消除用于平衡在不同频率或时钟相位工作的发起代理和目的代理之间的数据传输的昂贵的同步电路的缺点，如 在现有技术中。 本发明的装置组合了具有多级链的较慢级的链，其中每一级都包括一个简单的同步电路和一个异或门，用于接收从较快级链发送的事件数。 因此，较慢的数据不会错过更快的数据。

公开(公告)号：US08649210B2

公开(公告)日：2014-02-11

申请号：US13403689

申请日：2012-02-23

Applicant: Chih-Hsin Lin ,  Tsung-Huang Chen ,  Bing-Shiun Wang ,  Jen-Pin Su

Inventor： Chih-Hsin Lin ,  Tsung-Huang Chen ,  Bing-Shiun Wang ,  Jen-Pin Su

IPC: G11C11/00

CPC classification number: G11C7/22 ,  G06F13/1689 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1093

Abstract: A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock, and receives a double data rate data from the controller via the common bus according to a data strobe signal from the controller. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory.

Abstract translation: 提供双倍数据速率伪SRAM（DDR PSRAM）。 DDR PSRAM包括数据接收器，存储器和地址解码器。 数据接收器根据时钟通过公共总线从控制器接收第一单个数据速率数据，并且根据来自控制器的数据选通信号经由公共总线从控制器接收双数据速率数据。 地址解码器解码第一单个数据速率数据以获得存储器的地址。 数据接收器将双倍数据速率数据存储到存储器的地址中。