公开(公告)号：US20050106793A1

公开(公告)日：2005-05-19

申请号：US10718008

申请日：2003-11-19

Applicant: Zhong Dong ,  Chuck Jang ,  Chunchieh Huang

Inventor： Zhong Dong ,  Chuck Jang ,  Chunchieh Huang

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/336

CPC classification number: H01L29/511 ,  H01L21/28273

Abstract: An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell. In an alternative embodiment, after the middle, silicon nitride of the ONO structure is defined, another layer of intrinsic silicon is deposited, by way of for example, ALD. Heat and an oxidizing atmosphere are used to convert the second deposited, intrinsic silicon into thermally-grown, silicon dioxide. An ONO structure with two thermally-grown, and spaced apart, silicon oxide layers is thereby provided.

Abstract translation: 通过在氧化停止层上沉积本征硅来形成ONO型多晶硅绝缘体。 在一个实施方案中，氧化停止层是较低且导电掺杂的多晶硅层的氮化顶表面。 在一个实施例中，原子层沉积（ALD）用于精确控制沉积的本征硅的厚度。 使用热和氧化气氛将沉积的本征硅转化成热生长的二氧化硅。 氧化停止层阻碍更深的氧化。 在形成上部和导电掺杂的多晶硅层之前，进一步沉积氮化硅层和另外的氧化硅层以完成ONO结构。 在一个实施例中，下部和上部多晶硅层被图案化以分别限定电可重新编程的存储器单元的浮动栅极（FG）和控制栅极（CG）。 在替代实施例中，在中间形成ONO结构的氮化硅之后，通过例如ALD沉积另一层本征硅。 使用热和氧化气氛将第二沉积的本征硅转化成热生长的二氧化硅。 由此提供具有两个热生长和间隔开的氧化硅层的ONO结构。

公开(公告)号：US07229880B2

公开(公告)日：2007-06-12

申请号：US10718008

申请日：2003-11-19

Applicant: Zhong Dong ,  Chuck Jang ,  Chunchieh Huang

Inventor： Zhong Dong ,  Chuck Jang ,  Chunchieh Huang

IPC: H01L21/336

CPC classification number: H01L29/511 ,  H01L21/28273

Abstract: An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell. In an alternative embodiment, after the middle, silicon nitride of the ONO structure is defined, another layer of intrinsic silicon is deposited, by way of for example, ALD. Heat and an oxidizing atmosphere are used to convert the second deposited, intrinsic silicon into thermally-grown, silicon dioxide. An ONO structure with two thermally-grown, and spaced apart, silicon oxide layers is thereby provided.

Abstract translation: 通过在氧化停止层上沉积本征硅来形成ONO型多晶硅绝缘体。 在一个实施方案中，氧化停止层是较低且导电掺杂的多晶硅层的氮化顶表面。 在一个实施例中，原子层沉积（ALD）用于精确控制沉积的本征硅的厚度。 使用热和氧化气氛将沉积的本征硅转化成热生长的二氧化硅。 氧化停止层阻碍更深的氧化。 在形成上部和导电掺杂的多晶硅层之前，进一步沉积氮化硅层和另外的氧化硅层以完成ONO结构。 在一个实施例中，下部和上部多晶硅层被图案化以分别限定电可重新编程的存储器单元的浮动栅极（FG）和控制栅极（CG）。 在替代实施例中，在中间形成ONO结构的氮化硅之后，通过例如ALD沉积另一层本征硅。 使用热和氧化气氛将第二沉积的本征硅转化成热生长的二氧化硅。 由此提供具有两个热生长和间隔开的氧化硅层的ONO结构。

公开(公告)号：US07071115B2

公开(公告)日：2006-07-04

申请号：US10772932

申请日：2004-02-04

Applicant: Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

Inventor： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/44 ,  H01L21/76

CPC classification number: H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

Abstract: In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

公开(公告)号：US20050266628A1

公开(公告)日：2005-12-01

申请号：US11193150

申请日：2005-07-29

Applicant: Daniel Wang ,  Chunchieh Huang ,  Dong Kim

Inventor： Daniel Wang ,  Chunchieh Huang ,  Dong Kim

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/105 ,  H01L21/336

CPC classification number: H01L27/11526 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11546

Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

公开(公告)号：US20050170578A1

公开(公告)日：2005-08-04

申请号：US10772520

申请日：2004-02-04

Applicant: Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

Inventor： Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

IPC: H01L21/76 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11539 ,  H01L27/115 ,  H01L27/11526

Abstract: Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

Abstract translation: 非易失性存储器字线（160）形成为控制栅极结构（280）的侧壁上的侧壁间隔物。 每个控制栅极结构可以包含浮动和控制栅极（120,140）或一些其它元件。 在用于字线的导电层（160）被沉积之前，基座（340）形成为与控制栅极结构相邻。 基座将有助于形成将在上覆电介质（310）中蚀刻的接触开口（330.1），以形成与字线的接触。 基座可以是虚拟结构。 基座可以物理接触两个字线。

公开(公告)号：US06566196B1

公开(公告)日：2003-05-20

申请号：US10146979

申请日：2002-05-15

Applicant: Barbara Haselden ,  Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Chung Wai Leung ,  Kuei-Chang Tsai

Inventor： Barbara Haselden ,  Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Chung Wai Leung ,  Kuei-Chang Tsai

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  Y10S438/954

Abstract: In a nonvolatile memory, a floating gate (124) is covered with ONO (98), and a control gate polysilicon layer (124) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer (101) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion (98.2) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric (210) is therefore reduced. Other embodiments are also provided.

Abstract translation: 在非易失性存储器中，浮动栅极（124）被ONO（98）覆盖，并且在ONO上形成控制栅多晶硅层（124）。 在控制栅极被图案化之后，控制栅极侧壁被氧化以形成二氧化硅的保护层（101）。 该氧化物在ONO的氮化硅部分（98.2）的随后蚀刻期间保护控制栅极多晶硅。 因此，可以用各向同性蚀刻去除氮化硅。 因此，减小了对衬底隔离电介质（210）的潜在损害。 还提供了其他实施例。