公开(公告)号：US09047948B1

公开(公告)日：2015-06-02

申请号：US13548429

申请日：2012-07-13

申请人： John Dinh ,  Nad Edward Gilbert ,  Shane Hollmer ,  Derric Lewis ,  John Ross Jameson ,  Daniel C. Wang ,  Juan Pablo Saenz Echeverry

发明人： John Dinh ,  Nad Edward Gilbert ,  Shane Hollmer ,  Derric Lewis ,  John Ross Jameson ,  Daniel C. Wang ,  Juan Pablo Saenz Echeverry

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C11/5614 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0097

摘要： Structures and methods for control of an operating window of a programmable impedance element are disclosed herein. In one embodiment, a semiconductor memory device can include: (i) a memory array having a programmable impedance element; (ii) a register configured to be programmed with data that represents an erase verify value, a program verify value, and a read trip point resistance value, for the memory array; (iii) a controller configured to determine a mode of operation for the memory array; (iv) a register access circuit configured to read the register to obtain data that corresponds to the mode of operation; and (v) a voltage generator configured to generate a reference voltage based on the register data, where the reference voltage is used to perform an operation on the programmable impedance element corresponding to the mode of operation.

摘要翻译： 本文公开了用于控制可编程阻抗元件的操作窗口的结构和方法。 在一个实施例中，半导体存储器件可以包括：（i）具有可编程阻抗元件的存储器阵列; （ii）配置为对存储器阵列编程的表示擦除验证值，程序验证值和读取跳变点电阻值的寄存器; （iii）控制器，被配置为确定所述存储器阵列的操作模式; （iv）寄存器访问电路，被配置为读取所述寄存器以获得对应于所述操作模式的数据; 以及（v）电压发生器，被配置为基于所述寄存器数据产生参考电压，其中所述参考电压用于对与所述操作模式相对应的所述可编程阻抗元件执行操作。

公开(公告)号：US07071115B2

公开(公告)日：2006-07-04

申请号：US10772932

申请日：2004-02-04

申请人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

发明人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/44 ,  H01L21/76

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

公开(公告)号：US20080291723A1

公开(公告)日：2008-11-27

申请号：US11752711

申请日：2007-05-23

申请人： Daniel C. Wang ,  Yue-Song He

发明人： Daniel C. Wang ,  Yue-Song He

IPC分类号： G11C11/34 ,  H01L29/788

CPC分类号： G11C16/3404 ,  G11C16/3409

摘要： A dynamically variable source resistance is provided for each sector of a NOR-type Flash memory device. The variable source resistance of a given sector is set to a relatively low value (i.e., close to zero) during read operations. The variable source resistance is set to a relatively high impedance value (i.e., close to being an open circuit) during flash erase operations. The variable source resistance is set to a first intermediate resistance value at least during soft-programming where the first intermediate resistance value is one that raises VS and thus drives VGS below local threshold even for over-erased transistors of the sector that have a VGoff de-assertion voltage applied to their control gates for purpose of turning those transistors off. In one embodiment, the variable source resistance is set to a second intermediate resistance value during a testing mode that tests the extent to which the corresponding sector has been over-erased. The results of the testing mode are then used to intelligently optimize the number of transistors that are simultaneously soft-programmed in that sector during each Vt compaction cycle.

摘要翻译： 为NOR型闪存设备的每个扇区提供动态可变源电阻。 在读取操作期间将给定扇区的可变源电阻设置为相对较低的值（即接近于零）。 在闪速擦除操作期间，可变源电阻被设置为相对较高的阻抗值（即接近于开路）。 至少在软编程期间，可变源电阻值被设置为第一中间电阻值，其中第一中间电阻值是引起VS的值，因此驱动VGS低于本地阈值，即使对于具有VGoff de的扇区的过擦除晶体管 为了将这些晶体管关断，施加到它们的控制栅极的施加电压。 在一个实施例中，在测试相应扇区已经被擦除的程度的测试模式期间，将可变源电阻设置为第二中间电阻值。 然后使用测试模式的结果来智能优化在每个Vt压缩循环期间在该扇区中同时软编程的晶体管的数量。

公开(公告)号：US07300745B2

公开(公告)日：2007-11-27

申请号：US10772520

申请日：2004-02-04

申请人： Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

发明人： Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L27/11539 ,  H01L27/115 ,  H01L27/11526

摘要： Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

摘要翻译： 非易失性存储器字线（160）形成为控制栅极结构（280）的侧壁上的侧壁间隔物。 每个控制栅极结构可以包含浮动和控制栅极（120,140）或一些其它元件。 在用于字线的导电层（160）被沉积之前，基座（340）形成为与控制栅极结构相邻。 基座将有助于形成将在上覆电介质（310）中蚀刻的接触开口（330.1），以形成与字线的接触。 基座可以是虚拟结构。 基座可以物理接触两个字线。