公开(公告)号：US20130024832A1

公开(公告)日：2013-01-24

申请号：US13186241

申请日：2011-07-19

Applicant: Wen-Hao Chen ,  Zhe-Wei Jiang ,  Chung-Min Fu

Inventor： Wen-Hao Chen ,  Zhe-Wei Jiang ,  Chung-Min Fu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.

Abstract translation: 一种实用程序包括：被配置为检查集成电路的布局图案的制造设计（DFM）检查器，以及布局改变指令生成器，其被配置为基于由DFM检验器生成的结果生成布局改变指令。 DFM检查器和布局改变指令生成器体现在非暂时性的存储介质上。 布局改变指令指定布局图案之间的布局图案的标识符以及要在布局图案上执行的相应布局改变。

公开(公告)号：US20060230371A1

公开(公告)日：2006-10-12

申请号：US11099834

申请日：2005-04-06

Applicant: Jui-Jung Yan ,  Chung-Min Fu ,  Ricky Yang

Inventor： Jui-Jung Yan ,  Chung-Min Fu ,  Ricky Yang

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5081

Abstract: A system for defect simulation is provided. A defect layout generator generates a defect layout comprising a given number of spot defects of a given size. A processor first compares the defect layout and a provided circuit layout comprising a plurality of conductive regions. The processor further determines whether the spot defects are located on the conductive regions, and determines whether short-circuits and/or open circuits are caused by the spot defects in the conductive regions.

Abstract translation: 提供了一种用于缺陷模拟的系统。 缺陷布局生成器生成包括给定尺寸的给定数量的斑点缺陷的缺陷布局。 处理器首先比较缺陷布局和提供的包括多个导电区域的电路布局。 处理器还确定斑点缺陷是否位于导电区域上，并且确定短路和/或开路是否由导电区域中的斑点缺陷引起。

公开(公告)号：US08786094B2

公开(公告)日：2014-07-22

申请号：US13540464

申请日：2012-07-02

Applicant: Chung-Min Fu ,  Wen-Hao Chen ,  Dian-Hau Chen

Inventor： Chung-Min Fu ,  Wen-Hao Chen ,  Dian-Hau Chen

IPC: H01L23/50 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L21/768 ,  H01L21/76816 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/00

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality of second conductive lines comprises a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines.

Abstract translation: 公开了半导体器件及其制造方法。 在一个实施例中，半导体器件包括工件和在金属化层中设置在工件上的多个第一导电线。 多个第二导线设置在金属化层中的工件上方。 多个第二导电线在工件的横截面视图中包括比多个第一导电线的垂直高度更大的垂直高度。

公开(公告)号：US08601408B2

公开(公告)日：2013-12-03

申请号：US13269757

申请日：2011-10-10

Applicant: Huang-Yu Chen ,  Yuan-Te Hou ,  Chung-Min Fu ,  Chung-Hsing Wang ,  Wen-Hao Chen ,  Yi-Kan Cheng

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Chung-Min Fu ,  Chung-Hsing Wang ,  Wen-Hao Chen ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

公开(公告)号：US20130132913A1

公开(公告)日：2013-05-23

申请号：US13303374

申请日：2011-11-23

Applicant: Chung-Min FU ,  Yung-Fong LU ,  Wen-Ju YANG ,  Chin-Chang HSU

Inventor： Chung-Min FU ,  Yung-Fong LU ,  Wen-Ju YANG ,  Chin-Chang HSU

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70

Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

Abstract translation: 装置包括用于存储具有至少一个模板的模板库的机器可读存储介质。 该模板将包括通过多图案化IC的单层而形成的至少一个图案的第一布局图示。 该图案具有使用多个分别不同的光掩模形成的多个部分。 第一布局表示包括识别每个部分将要位于哪个光掩模上的数据。 电子设计自动化（EDA）工具包括被配置为接收电路的至少一部分的硬件描述语言表示并且生成具有多个多边形的电路的一部分的第二布局表示的处理器。 EDA工具具有匹配模块，其识别并输出多个部分中的一个或多个部分是否匹配多个多边形的子集的指示。

公开(公告)号：US20070187845A1

公开(公告)日：2007-08-16

申请号：US11695665

申请日：2007-04-03

Applicant: Chung-min Fu ,  Huang-Sheng Lin ,  Yu-Chyi Harn ,  Hsien-Wei Chen

Inventor： Chung-min Fu ,  Huang-Sheng Lin ,  Yu-Chyi Harn ,  Hsien-Wei Chen

IPC: H01L23/544 ,  H01L21/76

CPC classification number: H01L23/585 ,  H01L23/544 ,  H01L23/562 ,  H01L2223/5442 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.

Abstract translation: 具有形成在基板中的集成电路区域的半导体管芯包括：靠近集成电路区域设置在基板中的至少一个管芯拐角电路禁止（DCCF）区域; 以及形成在所述至少一个DCCF区域内的至少一个配准特征。 所述至少一个配准特征包括从由激光熔丝标记，对准标记和监视标记组成的组中选择的结构。

公开(公告)号：US20140001638A1

公开(公告)日：2014-01-02

申请号：US13540464

申请日：2012-07-02

Applicant: Chung-Min Fu ,  Wen-Hao Chen ,  Dian-Hau Chen

Inventor： Chung-Min Fu ,  Wen-Hao Chen ,  Dian-Hau Chen

IPC: H01L23/50 ,  H01L21/306

CPC classification number: H01L21/768 ,  H01L21/76816 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/00

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality of second conductive lines comprises a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines.

Abstract translation: 公开了半导体器件及其制造方法。 在一个实施例中，半导体器件包括工件和在金属化层中设置在工件上的多个第一导电线。 多个第二导线设置在金属化层中的工件上方。 多个第二导电线在工件的横截面视图中包括比多个第一导电线的垂直高度更大的垂直高度。

公开(公告)号：US20130212544A1

公开(公告)日：2013-08-15

申请号：US13477153

申请日：2012-05-22

Applicant: Chi-Yeh YU ,  Chung-Min FU ,  Ping-Heng YEH

Inventor： Chi-Yeh YU ,  Chung-Min FU ,  Ping-Heng YEH

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5045 ,  G06F17/5081

Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.

Abstract translation: 计算机实现的方法包括访问存储在有形的，非暂时的机器可读介质中的3D-IC模型，在计算机处理器中处理该模型以产生包含在操作下的3D-IC的多个点处的温度的温度图 条件; 识别电迁移（EM）额定因子，以及从处理器计算和输出表示每个点处的温度依赖EM电流约束的数据。

公开(公告)号：US20100275167A1

公开(公告)日：2010-10-28

申请号：US12708098

申请日：2010-02-18

Applicant: Chung-Min Fu ,  Yen-Pin Chen ,  Yung-Fong Lu

Inventor： Chung-Min Fu ,  Yen-Pin Chen ,  Yung-Fong Lu

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of designing an integrated circuit includes providing a standard cell database including a plurality of standard cells; providing an index file having cell-context information indexed to the plurality of standard cells; retrieving the cell-context information of one of the plurality of standard cells from the cell-context file; and applying the index information to a design of the integrated circuit.

Abstract translation: 设计集成电路的方法包括提供包括多个标准单元的标准单元数据库; 提供具有索引到所述多个标准单元的单元格上下文信息的索引文件; 从所述小区上下文文件中检索所述多个标准小区之一的小区上下文信息; 以及将所述索引信息应用于所述集成电路的设计。

公开(公告)号：US20090055782A1

公开(公告)日：2009-02-26

申请号：US11841509

申请日：2007-08-20

Applicant: Chung-Min Fu ,  Yi-Kan Cheng

Inventor： Chung-Min Fu ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method for designing and manufacturing integrated circuits is provided. The method includes providing a modeling parameter set for manufacturing an integrated circuit; dividing the modeling parameter set into time-dependent data and time-independent data; saving substantially all time-independent data into a design library; and saving substantially all time-dependent data into a design-for-manufacturing (DFM) data kit, wherein the DFM data kit is external to the design library.

Abstract translation: 提供了集成电路的设计和制造方法。 该方法包括提供用于制造集成电路的建模参数集; 将建模参数集划分为时间依赖数据和时间无关数据; 节省大量所有与时间无关的数据到设计库中; 并将大量所有时间相关数据节省到制造设计（DFM）数据套件中，其中DFM数据套件位于设计库的外部。