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    Dynamic timing adjustment in a circuit device
    11.
    发明申请
    Dynamic timing adjustment in a circuit device 有权
    电路设备中的动态时序调整

    公开(公告)号：US20070214377A1

    公开(公告)日：2007-09-13

    申请号：US11371142

    申请日：2006-03-08

    Applicant: Anis Jarrar ,  Colin MacDonald

    Inventor： Anis Jarrar ,  Colin MacDonald

    IPC: G06F1/12

    CPC classification number: G06F1/10

    Abstract: A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an output signal at an input of a second latch of the circuit device. The method additionally includes delaying a clock signal by a first delay to provide a first adjusted clock signal and delaying the clock signal by a second delay to provide a second adjusted clock signal. In one embodiment, the first delay and the second delay are based on the first operational characteristic. The method further includes latching the input signal at the first latch responsive to the first adjusted clock signal and latching the output signal at the second latch responsive to the second adjusted clock signal.

    Abstract translation: 一种方法包括在第一时间确定代表电路装置的操作速度的第一操作特性。 该方法还包括在电路装置的第一锁存器的输入处接收输入信号，并在电路装置的第二锁存器的输入处接收输出信号。 该方法还包括将时钟信号延迟第一延迟以提供第一调整时钟信号并延迟时钟信号第二延迟以提供第二调整时钟信号。 在一个实施例中，第一延迟和第二延迟基于第一操作特性。 该方法还包括响应于第一调整后的时钟信号而在第一锁存器处锁存输入信号，并响应于第二调整后的时钟信号将输出信号锁存在第二锁存器处。

    Circuit and method of controlling cache memory
    12.
    发明授权
    Circuit and method of controlling cache memory 有权
    控制缓存的电路及方法

    公开(公告)号：US06279083B1

    公开(公告)日：2001-08-21

    申请号：US09275617

    申请日：1999-03-24

    Applicant: Colin MacDonald

    Inventor： Colin MacDonald

    IPC: G06F1200

    CPC classification number: G06F12/0888

    Abstract: A memory controller (26) compares the current address and the previous address sent by a microprocessor (12). If the addresses are DRAM addresses and the current row address matches the previous row address, i.e. same DRAM page access, then the memory controller disables caching (28) of the same DRAM page access. The same DRAM page access disables caching because the same DRAM page access is not substantially longer than a cache access. A counter (50) and comparator (52) allows the memory controller to hold off some number of same DRAM page accesses before disabling caching to give time for the memory controller to set up to the new page.

    Abstract translation: 存储器控制器（26）比较由微处理器（12）发送的当前地址和以前的地址。 如果地址是DRAM地址，并且当前行地址与先前的行地址相匹配，即相同的DRAM页访问，则存储器控制器禁用相同DRAM页访问的高速缓存（28）。 相同的DRAM页面访问禁用高速缓存，因为相同的DRAM页面访问不比缓存访问长得多。 计数器（50）和比较器（52）允许存储器控制器在禁用高速缓存之前暂停一些数量相同的DRAM页面访问，以给存储器控制器设置到新页面的时间。

    LOW SWING FLIP-FLOP WITH REDUCED LEAKAGE SLAVE LATCH
    13.
    发明申请
    LOW SWING FLIP-FLOP WITH REDUCED LEAKAGE SLAVE LATCH 有权
    具有减少泄漏自动锁定的低开关翻转

    公开(公告)号：US20160072484A1

    公开(公告)日：2016-03-10

    申请号：US14481269

    申请日：2014-09-09

    Applicant: Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

    Inventor： Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

    IPC: H03K3/3562

    CPC classification number: H03K3/35625 ,  H03K3/0372

    Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

    Abstract translation: 数据处理系统包括用于在第一和第二电压下提供功率的第一和第二配电网络以及触发器。 第二电压小于第一电压。 触发器包括具有连接到第一配电网络的电力节点的主锁存器，数据信号输入端和以第一电压驱动的输出信号输出，以及具有与第一电源连接的电源节点的从锁存器 配电网络，耦合到主锁存器的输出的输入，由第一电压驱动的从锁存输出信号输出，以及具有与第二电压连接的功率节点的第一锁存逆变器的反馈电路，输入 耦合到主锁存器输出端，输出端提供由第二电压驱动的输出信号。

    Automatic synchronous-to-asynchronous software application converter
    14.
    发明授权
    Automatic synchronous-to-asynchronous software application converter 有权
    自动同步到异步软件应用转换器

    公开(公告)号：US08607206B2

    公开(公告)日：2013-12-10

    申请号：US13245388

    申请日：2011-09-26

    Applicant: Nathan T. Freeman ,  Colin Macdonald ,  Tim Tripcony

    Inventor： Nathan T. Freeman ,  Colin Macdonald ,  Tim Tripcony

    IPC: G06F9/44 ,  G06F9/45

    CPC classification number: G06F8/456 ,  G06F8/70

    Abstract: A computer-implemented method of generating output computer code, for an application executable via a server running application logic in communication with a client running a presentation layer for the application, from input computer code of a synchronous application in which logic and presentation layers run locally on a single computer. The output code runs asynchronously.

    Abstract translation: 一种用于生成输出计算机代码的计算机实现的方法，用于通过运行应用程序逻辑的应用程序可执行的应用程序，该应用程序逻辑与运行应用程序的表示层的客户端通过本地运行逻辑和表示层的同步应用程序的输入计算机代码 在一台电脑上 输出代码异步运行。

    Low pin count reset configuration
    15.
    发明授权
    Low pin count reset configuration 有权
    低引脚数复位配置

    公开(公告)号：US07420401B2

    公开(公告)日：2008-09-02

    申请号：US11453324

    申请日：2006-06-14

    Applicant: Colin MacDonald ,  Alan J. Carlin ,  Chris C. Dao

    Inventor： Colin MacDonald ,  Alan J. Carlin ,  Chris C. Dao

    IPC: H03K3/02

    CPC classification number: H03K19/1732 ,  G06F1/22

    Abstract: An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

    Abstract translation: 集成电路配置有用于指定集成电路内的电路的复位配置向量的引脚。 检测并利用耦合到引脚的低成本外部电阻器的电阻值来识别配置。 集成电路上的逻辑检测并利用电阻值对查找表中的配置向量进行索引。 然后根据索引的配置向量配置集成电路。

    Low pin count reset configuration
    16.
    发明申请
    Low pin count reset configuration 有权
    低引脚数复位配置

    公开(公告)号：US20070290731A1

    公开(公告)日：2007-12-20

    申请号：US11453324

    申请日：2006-06-14

    Applicant: Colin MacDonald ,  Alan J. Carlin ,  Chris C. Dao

    Inventor： Colin MacDonald ,  Alan J. Carlin ,  Chris C. Dao

    IPC: H03K3/02

    CPC classification number: H03K19/1732 ,  G06F1/22

    Abstract: An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

    Abstract translation: 集成电路配置有用于指定集成电路内的电路的复位配置向量的引脚。 检测并利用耦合到引脚的低成本外部电阻器的电阻值来识别配置。 集成电路上的逻辑检测并利用电阻值对查找表中的配置向量进行索引。 然后根据索引的配置向量配置集成电路。

    System and method for reducing the power consumption of clock systems
    17.
    发明申请
    System and method for reducing the power consumption of clock systems 有权
    降低时钟系统功耗的系统和方法

    公开(公告)号：US20070180410A1

    公开(公告)日：2007-08-02

    申请号：US11342747

    申请日：2006-01-30

    Applicant: Colin MacDonald ,  John Dalbey ,  Anis Jarrar

    Inventor： Colin MacDonald ,  John Dalbey ,  Anis Jarrar

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F2217/62 ,  G06F2217/78

    Abstract: A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed to reduce a current needed from the clock driver to drive the plurality of synchronous cells.

    Abstract translation: 一种设计集成电路的方法的系统识别由时钟驱动器驱动的集成电路的多个同步单元，其中多个同步单元是集成电路的先前放置的单元的子集。 执行同步单元的布置以减少从时钟驱动器驱动多个同步单元所需的电流。

    Deterministic prediction in an image processing system
    18.
    发明授权
    Deterministic prediction in an image processing system 有权

    公开(公告)号：US06999627B2

    公开(公告)日：2006-02-14

    申请号：US10025290

    申请日：2001-12-19

    Applicant: Colin MacDonald ,  Tamas Kovacs

    Inventor： Colin MacDonald ,  Tamas Kovacs

    IPC: G06K9/36

    CPC classification number: G06T9/004 ,  H04N19/42 ,  H04N19/44 ,  H04N19/91

    Abstract: Embodiments of the present invention relate to deterministic prediction in an image processing system. One aspect relates to an image processing system having a deterministic prediction decode unit for predicting individual pixels of an image based on a predetermined deterministic prediction algorithm. The deterministic prediction decode unit includes a look-up table, organized into four spatial phases, for storing values to be used by the predetermined deterministic prediction algorithm when converting a relatively low resolution image to a relatively higher resolution image. A prediction is made for a target pixel by accessing at least two of the four spatial phases of the look-up table to read at least two possible values of the target pixel. In one embodiment, the value of two target pixels can be provided within a same clock period, thus allowing for the decoding of two spatial phases with each access to the look-up table.

    Low swing flip-flop with reduced leakage slave latch
    19.
    发明授权
    Low swing flip-flop with reduced leakage slave latch 有权
    低摆幅触发器具有减少的漏电从器件锁存器

    公开(公告)号：US09425775B2

    公开(公告)日：2016-08-23

    申请号：US14481269

    申请日：2014-09-09

    Applicant: Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

    Inventor： Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

    IPC: H03K3/289 ,  H03K3/3562 ,  H03K3/037

    CPC classification number: H03K3/35625 ,  H03K3/0372

    Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

    Abstract translation: 数据处理系统包括用于在第一和第二电压下提供功率的第一和第二配电网络以及触发器。 第二电压小于第一电压。 触发器包括具有连接到第一配电网络的电力节点的主锁存器，数据信号输入端和以第一电压驱动的输出信号输出，以及具有与第一电源连接的电源节点的从锁存器 配电网络，耦合到主锁存器的输出的输入，由第一电压驱动的从锁存器输出信号输出，以及具有与第二电压连接的功率节点的第一锁存逆变器的反馈电路，输入 耦合到主锁存器输出端，输出端提供由第二电压驱动的输出信号。

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