公开(公告)号：US07609550B2

公开(公告)日：2009-10-27

申请号：US12099640

申请日：2008-04-08

Applicant: Amit Khanuja ,  Deepak Sabharwal

Inventor： Amit Khanuja ,  Deepak Sabharwal

IPC: G11C11/34

CPC classification number: H01L27/112 ,  G11C17/12

Abstract: A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.

Abstract translation: 用于扩散可编程ROM的紧凑型共享源线和位线架构。 在一个实施例中，ROM电路或实例包括被组织为行列阵列的多个存储单元。 共享源线与第一对相邻列相关联，共享源线保持在预定级别，其中相邻列中的存储单元的源极电耦合到共享源极线。 共享位线与第二对相邻列相关联，共享位线保持在预定电平，其中相邻列中的存储单元的漏极电耦合到共享位线。

公开(公告)号：US08031541B1

公开(公告)日：2011-10-04

申请号：US12346862

申请日：2008-12-31

Applicant: Vineet Kumar Sachan ,  Amit Khanuja ,  Deepak Sabharwal

Inventor： Vineet Kumar Sachan ,  Amit Khanuja ,  Deepak Sabharwal

IPC: G11C7/00

CPC classification number: G11C17/12 ,  G11C7/06

Abstract: Read only memory (ROM) with minimum leakage is provided. The ROM includes a read only memory array. The read only memory array includes a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. Another ROM includes a first transistor comprising a gate, electrically connected to a word line to provide a read signal, a drain, electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal. Further, a reference word line is electrically connected to a gate of a fourth transistor.

Abstract translation: 只提供具有最小泄漏的只读存储器（ROM）。 ROM包括只读存储器阵列。 只读存储器阵列包括第一晶体管，其中第一晶体管的漏极，源极，栅极和主体在空闲状态下电连接到逻辑零，以确保零结和次阈值漏电流。 另一ROM包括第一晶体管，其包括电连接到字线以提供读取信号的栅极，通过第二晶体管电连接到主位线的漏极。 第二晶体管包括电连接到第一解码电路的栅极，电连接到主位线的漏极。 第一参考位线电连接到第三晶体管的漏极，其中第三晶体管的栅极电连接到用于产生停止读信号的第二解码电路。 第二参考位线，其通过用于产生停止预充电信号的第一感测单元电连接到第一解码电路。 此外，参考字线电连接到第四晶体管的栅极。

公开(公告)号：US07929347B2

公开(公告)日：2011-04-19

申请号：US12577405

申请日：2009-10-12

Applicant: Amit Khanuja ,  Deepak Sabharwal

Inventor： Amit Khanuja ,  Deepak Sabharwal

IPC: G11C11/34

CPC classification number: H01L27/112 ,  G11C17/12

Abstract: A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.

Abstract translation: 用于扩散可编程ROM的紧凑型共享源线和位线架构。 在一个实施例中，ROM电路或实例包括被组织为行列阵列的多个存储单元。 共享源线与第一对相邻列相关联，共享源线保持在预定级别，其中相邻列中的存储单元的源极电耦合到共享源极线。 共享位线与第二对相邻列相关联，共享位线保持在预定电平，其中相邻列中的存储单元的漏极电耦合到共享位线。

公开(公告)号：US20110063893A1

公开(公告)日：2011-03-17

申请号：US12558816

申请日：2009-09-14

Applicant: Niranjan Behera ,  Deepak Sabharwal ,  Yong Zhang

Inventor： Niranjan Behera ,  Deepak Sabharwal ,  Yong Zhang

IPC: G11C11/00 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C11/412 ,  G11C11/413 ,  G11C2207/2227

Abstract: A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.

Abstract translation: 用于SRAM中的泄漏减少的源极偏置机构，其中SRAM单元被布置成多个扇区。 在待机模式下，多个扇区中的扇区中的SRAM单元被取消选择，并且向多个扇区的SRAM单元提供源极偏置电位。 在工作模式中，提供给多个扇区中选定扇区的SRAM单元的源极偏置电位被去激活，并且读出所选扇区内的物理行中的SRAM单元，而未被选择的扇区中剩余的SRAM单元继续 是源偏颇的。 提供给处于待机模式的SRAM单元的源极偏置电位可以根据控制信号的逻辑状态设置为不同的电压。

公开(公告)号：US20080212355A1

公开(公告)日：2008-09-04

申请号：US12099640

申请日：2008-04-08

Applicant: Amit Khanuja ,  Deepak Sabharwal

Inventor： Amit Khanuja ,  Deepak Sabharwal

IPC: G11C17/00

CPC classification number: H01L27/112 ,  G11C17/12

Abstract: A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.

Abstract translation: 用于扩散可编程ROM的紧凑型共享源线和位线架构。 在一个实施例中，ROM电路或实例包括被组织为行列阵列的多个存储单元。 共享源线与第一对相邻列相关联，共享源线保持在预定级别，其中相邻列中的存储单元的源极电耦合到共享源极线。 共享位线与第二对相邻列相关联，共享位线保持在预定电平，其中相邻列中的存储单元的漏极电耦合到共享位线。

公开(公告)号：US07061794B1

公开(公告)日：2006-06-13

申请号：US10813419

申请日：2004-03-30

Applicant: Deepak Sabharwal ,  Alexander Shubat

Inventor： Deepak Sabharwal ,  Alexander Shubat

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C8/08 ,  G11C11/417

Abstract: A source-biasing mechanism for leakage reduction in SRAM. In standby mode, wordlines are deselected and a source-biasing potential is provided to SRAM cells. In read mode, a selected wordline deactivates the source-biasing potential provided to the selected row of SRAM cells, whereas the remaining SRAM cells on the selected bitline column continue to be source-biased.

Abstract translation: 用于SRAM中泄漏减少的源偏置机制。 在待机模式下，取消选择字线，并向SRAM单元提供源极偏置电位。 在读取模式下，所选择的字线禁止提供给所选择的SRAM单元行的源极偏置电位，而所选位线列上的剩余SRAM单元继续源偏置。

公开(公告)号：US07002827B1

公开(公告)日：2006-02-21

申请号：US10364261

申请日：2003-02-10

Applicant: Deepak Sabharwal ,  Izak Kense ,  Alexander Shubat

Inventor： Deepak Sabharwal ,  Izak Kense ,  Alexander Shubat

IPC: G11C17/00

CPC classification number: G11C17/12 ,  H01L27/112 ,  H01L27/1122

Abstract: Methods and apparatuses in which a ROM memory array has virtual-grounded source lines programmed in layer physically higher than the diffusion layer. The ROM memory array may include a diffusion layer, one or more virtual-grounded source lines, and one or more bit lines. At least one of the virtual-grounded source lines is programmed with a layer physically higher than the diffusion layer.

Abstract translation: 其中ROM存储器阵列具有虚拟接地源极线的方法和装置，其物理上高于扩散层。 ROM存储器阵列可以包括扩散层，一个或多个虚拟接地源极线和一个或多个位线。 至少一个虚拟接地的源极线被物理地高于扩散层的层编程。

公开(公告)号：US06711092B1

公开(公告)日：2004-03-23

申请号：US10279428

申请日：2002-10-24

Applicant: Deepak Sabharwal

Inventor： Deepak Sabharwal

IPC: G11C800

CPC classification number: G11C7/222 ,  G11C7/1045 ,  G11C7/1072 ,  G11C8/18 ,  G11C2207/104

Abstract: A semiconductor memory with multiple timing loops for optimizing memory access operations. A clock generator circuit is provided for generating an internal memory clock based on an external clock or an input signal transition supplied to the memory device. The internal memory clock is operable to provide a timing reference with respect to a memory access operation based on a plurality of address signals. A timing loop selector is operable to select a particular timing loop responsive to at least one access margin signal. A shutdown circuit generates an access shutdown signal based on the selected timing loop that is optimized for a memory device of particular size, speed, etc.

Abstract translation: 具有多个定时环路的半导体存储器，用于优化存储器访问操作。 提供时钟发生器电路，用于基于提供给存储器件的外部时钟或输入信号转换来产生内部存储器时钟。 内部存储器时钟可操作以基于多个地址信号提供关于存储器访问操作的定时参考。 定时循环选择器可操作以响应于至少一个访问边缘信号来选择特定的定时环路。 关闭电路基于针对特定大小，速度等的存储器件优化的所选择的定时环路产生访问关闭信号。

公开(公告)号：US06587364B1

公开(公告)日：2003-07-01

申请号：US10128441

申请日：2002-04-23

Applicant: Adam Aleksan Kablanian ,  Deepak Sabharwal

Inventor： Adam Aleksan Kablanian ,  Deepak Sabharwal

IPC: G11C1604

CPC classification number: G11C17/12

Abstract: A compilable ROM architecture with enhanced performance characteristics, i.e., increased speed and lowered power consumption, wherein a plurality of memory locations are organized into one or more I/O blocks, each having a select number of bitlines. Each memory location is addressable by a row address and a column address. The data is stored in the ROM using a scrambled addressing scheme wherein a portion of the row and column addresses is interchanged in order to minimize bitline loading of the binary 0's.

Abstract translation: 具有增强的性能特性（即，增加的速度和降低的功耗）的可编译ROM架构，其中多个存储器位置被组织成一个或多个I / O块，每个I / O块具有选择数量的位线。 每个存储器位置都可以通过行地址和列地址进行寻址。 使用加扰寻址方案将数据存储在ROM中，其中行和列地址的一部分被互换，以便最小化二进制0的位线负载。

公开(公告)号：US20100027312A1

公开(公告)日：2010-02-04

申请号：US12577405

申请日：2009-10-12

Applicant: Amit Khanuja ,  Deepak Sabharwal

Inventor： Amit Khanuja ,  Deepak Sabharwal

IPC: G11C17/00 ,  G11C7/00

CPC classification number: H01L27/112 ,  G11C17/12

Abstract: A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.

Abstract translation: 用于扩散可编程ROM的紧凑型共享源线和位线架构。 在一个实施例中，ROM电路或实例包括被组织为行列阵列的多个存储单元。 共享源线与第一对相邻列相关联，共享源线保持在预定级别，其中相邻列中的存储单元的源极电耦合到共享源极线。 共享位线与第二对相邻列相关联，共享位线保持在预定电平，其中相邻列中的存储单元的漏极电耦合到共享位线。