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    Performance in predicting branches
    11.
    发明授权
    Performance in predicting branches 有权
    在预测分支中的表现

    公开(公告)号：US08972706B2

    公开(公告)日：2015-03-03

    申请号：US13116515

    申请日：2011-05-26

    申请人： Wen-Tzer T. Chen ,  Diane G. Flemming ,  William A. Maron ,  Mysore S. Srinivas ,  David B. Whitworth

    发明人： Wen-Tzer T. Chen ,  Diane G. Flemming ,  William A. Maron ,  Mysore S. Srinivas ,  David B. Whitworth

    IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38

    CPC分类号： G06F9/3844 ,  G06F9/38 ,  G06F9/3806 ,  G06F9/3848

    摘要： A data processing system and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.

    摘要翻译： 用于处理指令的数据处理系统和计算机程序产品。 所述指令由处理器单元处理，同时使用多个表中的第一表来预测在处理条件指令之后所述处理器单元所需的一组指令。 形成识别，即当使用第一表时正确预测指令集的成功率小于阈值数。 搜索由处理器单元处理的指令的序列，以搜索与用于识别何时使用多个表的一组标记中的标记相匹配的指令。 形成与标记相符的指令的标识。 识别由标记引用的多个表中的第二表。 第二个表用于代替第一个表。

    Autonomic I/O tracing and performance tuning
    12.
    发明授权
    Autonomic I/O tracing and performance tuning 失效
    自动I / O跟踪和性能调优

    公开(公告)号：US08539453B2

    公开(公告)日：2013-09-17

    申请号：US12827662

    申请日：2010-06-30

    申请人： Diane G. Flemming ,  Greg R. Mewhinney ,  Brian C. Twichell ,  David B. Whitworth

    发明人： Diane G. Flemming ,  Greg R. Mewhinney ,  Brian C. Twichell ,  David B. Whitworth

    IPC分类号： G06F9/44 ,  G06F3/00

    CPC分类号： G06F11/349 ,  G06F11/3409

    摘要： In an embodiment, a kernel performs autonomic input/output tracing and performance tuning. A first table is provided in a device driver framework and a second table in a kernel of a computer. An input/output device monitoring tool is provided in the device driver framework. A plurality of instructions in the kernel compares each value in the first table with each value in the second table. Responsive to a match of a value in the first table and a value in the second table, the kernel automatically runs a command line to perform a system trace, a component trace, or a tuning task. The first table is populated with a plurality of values calculated from a plurality of data in a plurality of device memories and in the controller memory and the second table is populated in accordance with a second plurality of inputs to the command line interface.

    摘要翻译： 在一个实施例中，内核执行自主输入/输出跟踪和性能调整。 在设备驱动程序框架和计算机的内核中的第二个表中提供了第一个表。 在设备驱动程序框架中提供输入/输出设备监视工具。 内核中的多个指令将第一个表中的每个值与第二个表中的每个值进行比较。 响应于第一个表中的值的匹配和第二个表中的值，内核将自动运行命令行以执行系统跟踪，组件跟踪或调整任务。 第一表填充有从多个设备存储器中的多个数据计算出的多个值，并且在控制器存储器中填充第二表，并且根据第二多个输入到命令行界面填充第二表。

    VARIABLE CACHE LINE SIZE MANAGEMENT
    13.
    发明申请
    VARIABLE CACHE LINE SIZE MANAGEMENT 有权
    可变缓存线尺寸管理

    公开(公告)号：US20130111135A1

    公开(公告)日：2013-05-02

    申请号：US13286507

    申请日：2011-11-01

    申请人： Robert H. Bell, JR. ,  Wen-Tzer T. Chen ,  Diane G. Flemming ,  Hong L. Hua ,  William A. Maron ,  Mysore S. Srinivas

    发明人： Robert H. Bell, JR. ,  Wen-Tzer T. Chen ,  Diane G. Flemming ,  Hong L. Hua ,  William A. Maron ,  Mysore S. Srinivas

    IPC分类号： G06F12/08

    CPC分类号： G06F12/08 ,  G06F12/0811 ,  G06F12/0897

    摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.

    摘要翻译： 根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。 该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小 对应于较低级别缓存的高速缓存行大小。 该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。

    SYMMETRIC MULTI-PROCESSOR LOCK TRACING
    14.
    发明申请
    SYMMETRIC MULTI-PROCESSOR LOCK TRACING 失效
    对称多处理器锁定

    公开(公告)号：US20110113406A1

    公开(公告)日：2011-05-12

    申请号：US12616005

    申请日：2009-11-10

    申请人： Diane G. Flemming ,  Eric P. Fried ,  Greg R. Mewhinney ,  David B. Whitworth

    发明人： Diane G. Flemming ,  Eric P. Fried ,  Greg R. Mewhinney ,  David B. Whitworth

    IPC分类号： G06F9/44 ,  G06F9/30

    CPC分类号： G06F11/3636 ,  G06F11/3404 ,  G06F11/3409 ,  G06F11/3471 ,  G06F2201/865 ,  G06F2201/885

    摘要： A symmetric multi-processor SMP system includes an SMP processor and operating system OS software that performs automatic SMP lock tracing analysis on an executing application program. System administrators, users or other entities initiate an automatic SMP lock tracing analysis. A particular thread of the executing application program requests and obtains a lock for a memory address pointer. A subsequent thread requests the same memory address pointer lock prior to the particular thread release of that lock. The subsequent thread begins to spin waiting for the release of that address pointer lock. When the subsequent thread reaches a predetermined maximum amount of wait time, MAXSPIN, a lock testing tool in the kernel of the OS detects the MAXSPIN condition. The OS performs a test to determine if the subsequent thread and address pointer lock meet the list of criteria set during initiation of the automatic lock trace method. The OS initiates an SMP lock trace capture automatically if all criteria or the arguments of the lock trace method are met. System administrators, software programmers, users or other entities interpret the results of the SMP lock tracing method that the OS stores in a trace table to determine performance improvements for the executing application program.

    摘要翻译： 对称多处理器SMP系统包括一个SMP处理器和操作系统OS软件，对执行的应用程序执行自动SMP锁跟踪分析。 系统管理员，用户或其他实体启动自动SMP锁跟踪分析。 执行应用程序的特定线程请求并获得用于存储器地址指针的锁。 随后的线程在该锁的特定线程释放之前请求相同的内存地址指针锁。 随后的线程开始旋转等待释放该地址指针锁。 当后续线程达到预定的最大等待时间时，MAXSPIN，OS内核中的锁定测试工具将检测MAXSPIN条件。 OS执行测试以确定后续线程和地址指针锁是否符合在启动自动锁定跟踪方法期间设置的条件列表。 如果符合锁跟踪方法的所有条件或参数，OS将自动启动SMP锁跟踪捕获。 系统管理员，软件程序员，用户或其他实体解释OS存储在跟踪表中的SMP锁跟踪方法的结果，以确定执行的应用程序的性能改进。

    Sharing a kernel of an operating system among logical partitions
    15.
    发明授权
    Sharing a kernel of an operating system among logical partitions 有权
    在逻辑分区之间共享操作系统的内核

    公开(公告)号：US09189291B2

    公开(公告)日：2015-11-17

    申请号：US11301113

    申请日：2005-12-12

    申请人： Andrew Dunshea ,  Diane G. Flemming

    发明人： Andrew Dunshea ,  Diane G. Flemming

    IPC分类号： G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00 ,  G06F9/50 ,  G06F9/445

    CPC分类号： G06F9/5077 ,  G06F8/60

    摘要： Sharing a kernel of an operating system among logical partitions, including installing in a partition manager a kernel of a type used by a plurality of logical partitions; installing in the partition manager generic data structures specifying computer resources assigned to each of the plurality of logical partitions; and providing, by the kernel to the logical partitions, kernel services in dependence upon the generic data structures.

    摘要翻译： 在逻辑分区之间共享操作系统的内核，包括在分区管理器中安装由多个逻辑分区使用的类型的内核; 在所述分区管理器中安装指定分配给所述多个逻辑分区中的每一个的计算机资源的通用数据结构; 并且由内核向逻辑分区提供依赖于通用数据结构的内核服务。

    Mixed operating performance modes including a shared cache mode
    16.
    发明授权
    Mixed operating performance modes including a shared cache mode 有权

    公开(公告)号：US08695011B2

    公开(公告)日：2014-04-08

    申请号：US13458769

    申请日：2012-04-27

    申请人： Diane G. Flemming ,  William A. Maron ,  Ram Raghavan ,  Satya Prakash Sharma ,  Mysore S. Srinivas

    发明人： Diane G. Flemming ,  William A. Maron ,  Ram Raghavan ,  Satya Prakash Sharma ,  Mysore S. Srinivas

    IPC分类号： G06F9/46 ,  G06F1/00 ,  G06F13/00

    CPC分类号： G06F9/5077

    摘要： Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.

    Managing rollback in a transactional memory environment
    17.
    发明授权
    Managing rollback in a transactional memory environment 有权
    在事务性内存环境中管理回滚

    公开(公告)号：US08539281B2

    公开(公告)日：2013-09-17

    申请号：US13451266

    申请日：2012-04-19

    申请人： Wen-Tzer T. Chen ,  Diane G. Flemming ,  William A. Maron ,  Mysore S. Srinivas ,  David B. Whitworth

    发明人： Wen-Tzer T. Chen ,  Diane G. Flemming ,  William A. Maron ,  Mysore S. Srinivas ,  David B. Whitworth

    IPC分类号： G06F11/00

    CPC分类号： G06F9/528 ,  G06F9/467

    摘要： According to one aspect of the present disclosure, a method and technique for managing rollback in a transactional memory environment is disclosed. The method includes, responsive to detecting a begin transaction directive by a processor supporting transactional memory processing, detecting an access of a first memory location not needing rollback and indicating that the first memory location does not need to be rolled back while detecting an access to a second memory location and indicating that a rollback will be required. The method also includes, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omitting a rollback of the first memory location while performing rollback on the second memory location.

    摘要翻译： 根据本公开的一个方面，公开了一种用于在事务存储器环境中管理回滚的方法和技术。 该方法包括：响应于由支持事务性存储器处理的处理器检测开始事务指令，检测不需要回滚的第一存储器位置的访问，并指示第一存储器位置不需要回滚，同时检测到对 第二个内存位置，并指示需要回滚。 该方法还包括：响应于在开始事务指令之后检测到结束事务指令和需要回滚的冲突，在第二存储器位置上执行回滚的同时省略第一存储器位置的回滚。

    Assigning cache priorities to virtual/logical processors and partitioning a cache according to such priorities
    19.
    发明授权
    Assigning cache priorities to virtual/logical processors and partitioning a cache according to such priorities 失效
    将缓存优先级分配给虚拟/逻辑处理器，并根据这些优先级对高速缓存进行分区

    公开(公告)号：US08301840B2

    公开(公告)日：2012-10-30

    申请号：US12637891

    申请日：2009-12-15

    申请人： Vaijayanthimala K. Anand ,  Diane G. Flemming ,  William A. Maron ,  Mysore S. Srinivas

    发明人： Vaijayanthimala K. Anand ,  Diane G. Flemming ,  William A. Maron ,  Mysore S. Srinivas

    IPC分类号： G06F12/12

    CPC分类号： G06F12/0895 ,  G06F9/5022 ,  G06F9/5077 ,  G06F12/126 ,  G06F2209/5021

    摘要： Mechanisms are provided, for implementation in a data processing system having at least one physical processor and at least one associated cache memory, for allocating cache resources of the at least one cache memory to virtual processors of the data processing system. The mechanisms identify a plurality of high priority virtual processors in the data processing system. The mechanisms further determine a percentage of cache lines of the at least one cache memory to be assigned to high priority virtual processors. Moreover, the mechanisms mark a portion of the cache lines in the at least one cache memory as being evictable by only high priority virtual processors based on the determined percentage of cache lines to be assigned to high priority virtual processors. The marked portion of the cache lines cannot be evicted by lower priority virtual processors having a priority lower than the high priority virtual processors.

    摘要翻译： 提供了用于在具有至少一个物理处理器和至少一个相关联的高速缓冲存储器的数据处理系统中实现的机制，用于将至少一个高速缓冲存储器的高速缓存资源分配给数据处理系统的虚拟处理器。 该机制识别数据处理系统中的多个高优先级虚拟处理器。 这些机制进一步确定要分配给高优先级虚拟处理器的至少一个高速缓冲存储器的高速缓存行的百分比。 此外，机制将所述至少一个高速缓冲存储器中的高速缓存行的一部分标记为仅基于所分配给高优先级虚拟处理器的高速缓存行的确定百分比仅被高优先级的虚拟处理器驱逐。 高速缓存行的标记部分不能被优先级低于高优先级虚拟处理器的较低优先级的虚拟处理器驱逐。