公开(公告)号：US07195933B2

公开(公告)日：2007-03-27

申请号：US11157534

申请日：2005-06-21

Applicant: Sang-Wook Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Joo-Chan Kim ,  Kook-Min Kim ,  Eui-Youl Ryu

Inventor： Sang-Wook Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Joo-Chan Kim ,  Kook-Min Kim ,  Eui-Youl Ryu

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

Abstract translation: 具有提高测量可靠性的测量图案的半导体器件以及使用测量图案测量半导体器件的方法。 半导体器件包括具有形成集成电路的芯片面积的半导体衬底和围绕芯片区域的划线区域。 半导体器件还包括形成在划线区域中的测量图案，并具有包括测量光束投射的光束区域的表面截面面积和形成在测量图案中的虚拟图案，以减小测量图案的表面截面面积 。 虚拟图案的表面截面积占射束面积的表面截面面积的约5％至约15％。

公开(公告)号：US07081380B2

公开(公告)日：2006-07-25

申请号：US10782782

申请日：2004-02-23

Applicant: Don-Woo Lee ,  Chul-Soon Kwon ,  Chang-Yup Lee

Inventor： Don-Woo Lee ,  Chul-Soon Kwon ,  Chang-Yup Lee

IPC: H01L21/8238

CPC classification number: H01L29/66825 ,  H01L21/7684

Abstract: A method of forming a conductive pattern of a semiconductor device includes forming a conductive layer is on a substrate, forming a polishing protection layer on the substrate including over the conductive layer, and forming a step compensation layer on the polishing protection layer to reduce the step presented by the layer that is the polishing protection layer. The conductive layer is the exposed by removing select portions of the step compensation layer and the polishing protection layer. The conductive pattern is ultimately formed on the substrate by etching the exposed conductive layer. By planarization the intermediate structure several times once the step compensation layer is formed, a highly uniform conductive layer is sure to be formed.

Abstract translation: 形成半导体器件的导电图案的方法包括在基板上形成导电层，在包括在导电层上的衬底上形成抛光保护层，并在抛光保护层上形成台阶补偿层，以减少步骤 由抛光保护层的层呈现。 通过去除步进补偿层和抛光保护层的选择部分来暴露导电层。 通过蚀刻暴露的导电层，最终在衬底上形成导电图案。 通过中间结构的平面化，一旦形成了阶梯补偿层，就可以确保形成高度均匀的导电层。

公开(公告)号：US06974748B2

公开(公告)日：2005-12-13

申请号：US10920158

申请日：2004-08-18

Applicant: Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

Inventor： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC: H01L27/10 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11539

Abstract: A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

公开(公告)号：US20050035433A1

公开(公告)日：2005-02-17

申请号：US10858926

申请日：2004-06-02

Applicant: Sang-Wook Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Joo-Chan Kim ,  Kook-Min Kim ,  Eui-Youl Ryu

Inventor： Sang-Wook Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Joo-Chan Kim ,  Kook-Min Kim ,  Eui-Youl Ryu

IPC: H01L21/66 ,  H01L21/027 ,  H01L21/822 ,  H01L23/544 ,  H01L27/04

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

公开(公告)号：US6060927A

公开(公告)日：2000-05-09

申请号：US119971

申请日：1998-07-21

Applicant: Don-Woo Lee

Inventor： Don-Woo Lee

IPC: H03K3/356 ,  H03K3/037 ,  H03K19/00 ,  H03K19/096

CPC classification number: H03K19/0963

Abstract: A high-speed flip-flop is provided that implements a low power consumption and a high-speed response caused by an interior capacitance reduction. A D flip-flop includes a first latch that receives a clock signal and a data signal to produce a first output signal. A second latch receives the first output signal and the clock signal to produce a second output signal. A third latch receives the second output signal and the clock signal to produce a third output signal. An inverter receives the third output signal to produce the data signal on a rising or falling edge of the clock signal. The first and second latches are preferably ratioed latches having series coupled pull-up and pull-down elements. The third latch is preferably a clock operated latch.

Abstract translation: 提供了一种实现低功耗和由内部电容降低引起的高速响应的高速触发器。 A触发器包括第一锁存器，其接收时钟信号和数据信号以产生第一输出信号。 第二锁存器接收第一输出信号和时钟信号以产生第二输出信号。 第三锁存器接收第二输出信号和时钟信号以产生第三输出信号。 逆变器接收第三输出信号以在时钟信号的上升沿或下降沿产生数据信号。 第一和第二锁存器优选地是具有串联耦合上拉和下拉元件的比例锁存器。 第三锁存器优选地是时钟操作的锁存器。

公开(公告)号：US07544991B2

公开(公告)日：2009-06-09

申请号：US11698067

申请日：2007-01-26

Applicant: Jin-Woo Kim ,  Jong-Hyon Ahn ,  Don-Woo Lee

Inventor： Jin-Woo Kim ,  Jong-Hyon Ahn ,  Don-Woo Lee

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/42336 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11553 ,  H01L29/7885

Abstract: A non-volatile memory device and methods of manufacturing and operating the same are provided. In a method of manufacturing a non-volatile memory device, a substrate having a stepped portion that may include a first horizontal face, a second horizontal face lower than the first horizontal face, and a vertical face connected between the first and second horizontal faces may be prepared. A first impurity region may be formed under the first horizontal face. A tunnel insulation layer may be continuously formed on the vertical face and the second horizontal face. A floating gate electrode having a tip higher than the first horizontal face may be formed on the tunnel insulation layer. A dielectric layer may be formed on the floating gate electrode. The floating gate electrode may be covered with a control gate electrode. A second impurity region horizontally spaced apart from the floating gate electrode may be formed under the second horizontal face.

Abstract translation: 提供了一种非易失性存储器件及其制造和操作方法。 在制造非易失性存储器件的方法中，具有阶梯部分的衬底可以包括第一水平面，比第一水平面低的第二水平面和连接在第一和第二水平面之间的垂直面， 准备好 可以在第一水平面下方形成第一杂质区。 隧道绝缘层可以在垂直面和第二水平面上连续地形成。 具有尖端高于第一水平面的浮栅电极可以形成在隧道绝缘层上。 可以在浮栅电极上形成电介质层。 浮栅电极可以用控制栅电极覆盖。 可以在第二水平面下方形成与浮栅电极水平间隔开的第二杂质区域。

公开(公告)号：US06800525B2

公开(公告)日：2004-10-05

申请号：US10631186

申请日：2003-07-31

Applicant: Eui-Youl Ryu ,  Jae-Min Yu ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Sag-Wook Park ,  Joo-Chan Kim ,  Kook-Min Kim ,  Min-Soo Cho ,  Chul-Soon Kwon

Inventor： Eui-Youl Ryu ,  Jae-Min Yu ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Sag-Wook Park ,  Joo-Chan Kim ,  Kook-Min Kim ,  Min-Soo Cho ,  Chul-Soon Kwon

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The method of manufacturing a split gate flash memory device includes the steps of (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) etching the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) etching the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film remained, and exposing the first conductive film provided in a lower part thereof; and (h) etching the first dielectric film and the first conductive film exposed by the removal of the second dielectric film using the fourth dielectric film as an etch mask, and forming a second gate dielectric film and a word line.

公开(公告)号：US06392475B1

公开(公告)日：2002-05-21

申请号：US09783586

申请日：2001-02-15

Applicant: Don-Woo Lee

Inventor： Don-Woo Lee

IPC: H03F102

CPC classification number: H03F3/45968 ,  H03F3/005 ,  H03F3/45475 ,  H03F2203/45551

Abstract: The present invention relates to an offset compensation apparatus in a differential amplifier circuit and an offset compensation method thereof that can compensate an offset in a differential amplifier circuit separately for each input signal. The offset compensation device preferably selectively couples a capacitor to an input of a differential amplifier to store an offset voltage. The offset compensation method preferably can operate by detecting an offset of the differential amplifier circuit, by storing the offset, by directly inputting the result of compensating the offset voltage for an input voltage into the differential amplifier and by outputting the output voltage corresponding to the input voltage without the offset voltage included. The differential amplifier circuit and the offset compensation method can further include an additional output stage coupled to a load.

Abstract translation: 本发明涉及一种差分放大电路中的偏移补偿装置及其偏移补偿方法，该方法能够针对每个输入信号分别补偿差分放大器电路中的偏移。 偏移补偿装置优选地将电容器选择性地耦合到差分放大器的输入端以存储偏移电压。 偏移补偿方法优选地可以通过直接输入将输入电压的偏移电压补偿到差分放大器中并通过输出对应于输入的输出电压的结果来存储偏移来检测差分放大器电路的偏移 电压不包括偏移电压。 差分放大器电路和偏移补偿方法还可以包括耦合到负载的附加输出级。