公开(公告)号：US20050042828A1

公开(公告)日：2005-02-24

申请号：US10920158

申请日：2004-08-18

申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

摘要翻译： 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

公开(公告)号：US20050064661A1

公开(公告)日：2005-03-24

申请号：US10874579

申请日：2004-06-24

申请人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

发明人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

摘要翻译： 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

公开(公告)号：US07375391B2

公开(公告)日：2008-05-20

申请号：US11246590

申请日：2005-10-11

申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

摘要翻译： 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

公开(公告)号：US07205194B2

公开(公告)日：2007-04-17

申请号：US10874579

申请日：2004-06-24

申请人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

发明人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

摘要翻译： 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

公开(公告)号：US20060027858A1

公开(公告)日：2006-02-09

申请号：US11246590

申请日：2005-10-11

申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

摘要翻译： 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

公开(公告)号：US06974748B2

公开(公告)日：2005-12-13

申请号：US10920158

申请日：2004-08-18

申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

公开(公告)号：US06800525B2

公开(公告)日：2004-10-05

申请号：US10631186

申请日：2003-07-31

申请人： Eui-Youl Ryu ,  Jae-Min Yu ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Sag-Wook Park ,  Joo-Chan Kim ,  Kook-Min Kim ,  Min-Soo Cho ,  Chul-Soon Kwon

发明人： Eui-Youl Ryu ,  Jae-Min Yu ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Sag-Wook Park ,  Joo-Chan Kim ,  Kook-Min Kim ,  Min-Soo Cho ,  Chul-Soon Kwon

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The method of manufacturing a split gate flash memory device includes the steps of (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) etching the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) etching the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film remained, and exposing the first conductive film provided in a lower part thereof; and (h) etching the first dielectric film and the first conductive film exposed by the removal of the second dielectric film using the fourth dielectric film as an etch mask, and forming a second gate dielectric film and a word line.

公开(公告)号：US06924505B2

公开(公告)日：2005-08-02

申请号：US10858926

申请日：2004-06-02

申请人： Sang-Wook Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Joo-Chan Kim ,  Kook-Min Kim ,  Eui-Youl Ryu

发明人： Sang-Wook Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Joo-Chan Kim ,  Kook-Min Kim ,  Eui-Youl Ryu

IPC分类号： H01L21/66 ,  H01L21/027 ,  H01L21/822 ,  H01L23/544 ,  H01L27/04 ,  H01L23/58

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

摘要翻译： 具有提高测量可靠性的测量图案的半导体器件以及使用测量图案测量半导体器件的方法。 半导体器件包括具有形成集成电路的芯片面积的半导体衬底和围绕芯片区域的划线区域。 半导体器件还包括形成在划线区域中的测量图案，并具有包括测量光束投射的光束区域的表面截面面积和形成在测量图案中的虚拟图案，以减小测量图案的表面截面面积 。 虚拟图案的表面截面积占射束面积的表面截面面积的约5％至约15％。

公开(公告)号：US20050230786A1

公开(公告)日：2005-10-20

申请号：US11157534

申请日：2005-06-21

申请人： Sang-Wook Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Joo-Chan Kim ,  Kook-Min Kim ,  Eui-Youl Ryu

发明人： Sang-Wook Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Joo-Chan Kim ,  Kook-Min Kim ,  Eui-Youl Ryu

IPC分类号： H01L21/66 ,  H01L21/027 ,  H01L21/822 ,  H01L23/544 ,  H01L27/04 ,  H01L21/46

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

公开(公告)号：US07195933B2

公开(公告)日：2007-03-27

申请号：US11157534

申请日：2005-06-21

申请人： Sang-Wook Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Joo-Chan Kim ,  Kook-Min Kim ,  Eui-Youl Ryu

发明人： Sang-Wook Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  Jin-Woo Kim ,  Jae-Hyun Park ,  Yong-Hee Kim ,  Don-Woo Lee ,  Dai-Geun Kim ,  Joo-Chan Kim ,  Kook-Min Kim ,  Eui-Youl Ryu

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

摘要翻译： 具有提高测量可靠性的测量图案的半导体器件以及使用测量图案测量半导体器件的方法。 半导体器件包括具有形成集成电路的芯片面积的半导体衬底和围绕芯片区域的划线区域。 半导体器件还包括形成在划线区域中的测量图案，并具有包括测量光束投射的光束区域的表面截面面积和形成在测量图案中的虚拟图案，以减小测量图案的表面截面面积 。 虚拟图案的表面截面积占射束面积的表面截面面积的约5％至约15％。