中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

36 records (took 0.031 seconds)

    High data rate interface with improved link control
    11.
    发明申请
    High data rate interface with improved link control 有权
    高数据速率接口，改善了链路控制

    公开(公告)号：US20050135390A1

    公开(公告)日：2005-06-23

    申请号：US10987123

    申请日：2004-11-12

    Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    IPC: H04L12/28 ,  H04L12/56 ,  H04L12/64 ,  H04L29/06 ,  H04L29/08 ,  H04M1/725

    CPC classification number: H04L65/4069 ,  H04L12/6418 ,  H04L29/06 ,  H04L29/06027 ,  H04L65/1069 ,  H04L65/80 ,  H04L69/12 ,  H04L69/18 ,  H04L69/22 ,  H04L69/24 ,  H04L69/324 ,  H04M1/72527 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/26

    Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

    Hazard-free circuitry for determining full and empty conditions in first-in-first-out memory
    12.
    发明授权
    Hazard-free circuitry for determining full and empty conditions in first-in-first-out memory 失效
    用于确定先进先出存储器中的全部和空白条件的无危险电路

    公开(公告)号：US5491659A

    公开(公告)日：1996-02-13

    申请号：US372480

    申请日：1995-01-13

    Applicant: Dave Howarter ,  George Wiley

    Inventor： Dave Howarter ,  George Wiley

    IPC: G06F5/10 ,  G06F5/14 ,  G11C7/00

    CPC classification number: G06F5/14 ,  G06F2205/102

    Abstract: In a first-in-first out memory, at least one data item is stored, and a write counter is incremented in response to the storing of each data item as it is stored into the memory. A full condition counter is also incremented in response to the writing of each data item. The at least one data item is also read from the memory, and a read counter is incremented in response to the reading of each data item from the memory. An empty condition counter is also incremented in response to the reading of each data item from the memory. In order to assure that the empty and full flag signals are not generated simultaneously, the full flag signal is generated in response to a count within the full condition counter that leads a count within the empty condition counter by a first prescribed difference. The empty flag signal is generated in response to the count within the full condition counter lagging the count within the empty condition counter by a second prescribed difference. As a result, the full flag signal and the empty flag signal are never simultaneously generated so long as the full condition counter and the empty condition counter each have at least one more state than the read counter and the write counter.

    Abstract translation: 在先进先出存储器中，存储至少一个数据项，并且响应于存储在存储器中的每个数据项的存储而增加写计数器。 响应于每个数据项的写入，全状态计数器也递增。 还从存储器读取至少一个数据项，并且响应于从存储器读取每个数据项而增加读计数器。 响应于从存储器读取每个数据项，空条件计数器也递增。 为了确保空标志信号和全标志信号不同时产生，响应于在空状态计数器内的计数引起第一规定差的全状态计数器内的计数，产生全标志信号。 响应于在完全状态计数器内的计数使空条件计数器中的计数器滞后第二规定的差值而产生空标志信号。 结果，只要全状态计数器和空状态计数器都具有比读计数器和写计数器至少多一个状态，则不会同时产生全标志信号和空标志信号。

    Multiple Transmitter System and Method
    14.
    发明申请
    Multiple Transmitter System and Method 有权
    多发射机系统和方法

    公开(公告)号：US20090225873A1

    公开(公告)日：2009-09-10

    申请号：US12042362

    申请日：2008-03-05

    Applicant: Chulkyu Lee ,  Anosh Davierwalla ,  George Wiley

    Inventor： Chulkyu Lee ,  Anosh Davierwalla ,  George Wiley

    IPC: H04B3/00

    CPC classification number: H04L25/0272 ,  H04L25/49

    Abstract: Systems and methods of data transmission are disclosed. In an embodiment, at least two transmitters are selectively activated and at least one transmitter is deactivated at a serial interface to transmit data via at least two distinct lines.

    Abstract translation: 公开了数据传输的系统和方法。 在一个实施例中，选择性地激活至少两个发射机，并且至少一个发射机在串行接口处被去激活，以经由至少两条不同的线路传输数据。

    MOBILE DEVICE INTERFACE FOR INPUT DEVICES
    16.
    发明申请
    MOBILE DEVICE INTERFACE FOR INPUT DEVICES 有权
    用于输入设备的移动设备接口

    公开(公告)号：US20060223581A1

    公开(公告)日：2006-10-05

    申请号：US11277916

    申请日：2006-03-29

    Applicant: Paul Jacobs ,  George Wiley ,  Franklin Antonio

    Inventor： Paul Jacobs ,  George Wiley ,  Franklin Antonio

    IPC: H04B1/38 ,  H04M1/00

    CPC classification number: H04M1/72527 ,  H04B1/38 ,  H04M1/6058 ,  H04M2250/18 ,  H04W92/08

    Abstract: A mobile electronic device includes an earphone/microphone port, an I/O circuit to receive a modulated data signal from data input devices via the earphone/microphone port, and a processor unit programmed to extract data from the modulated data signal. The processor unit (or the I/O circuit) detects connection of a device to an earphone/microphone connector of the mobile electronic device and determines whether the connected device is a data input device. If the connected device is a data input device, the processor unit is programmed to extract data from modulated data signals generated by data input device.

    Abstract translation: 移动电子设备包括耳机/麦克风端口，经由耳机/麦克风端口从数据输入设备接收调制数据信号的I / O电路，以及被编程为从调制数据信号提取数据的处理器单元。 处理器单元（或I / O电路）检测设备与移动电子设备的耳机/麦克风连接器的连接，并确定连接的设备是否是数据输入设备。 如果连接的设备是数据输入设备，则处理器单元被编程为从由数据输入设备生成的调制数据信号中提取数据。

    Digital data interface device message format
    17.
    发明申请
    Digital data interface device message format 有权
    数字数据接口设备消息格式

    公开(公告)号：US20060179164A1

    公开(公告)日：2006-08-10

    申请号：US11285389

    申请日：2005-11-23

    Applicant: Behnam Katibian ,  George Wiley

    Inventor： Behnam Katibian ,  George Wiley

    IPC: G06F3/00

    CPC classification number: H04N21/43632 ,  H04M1/0214 ,  H04N21/41407 ,  H04N21/4223

    Abstract: The present invention provides a digital data interface device message format that describes command and response messages to be exchanged between a digital device having a system controller and a digital data interface device. The digital data interface device includes a message interpreter, content module and a control module. The digital data interface device may include an MDDI link controller. The digital data interface device can be used by a cellular telephone to control a peripheral device, such as a camera, bar code reader, image scanner, audio device or other sensor. The digital data interface device message format includes a transaction identification field, a count field, a command identification field and a status field. Optionally, the message format can include a data field. When an MDDI link is used, a digital data interface device message can be included in an MDDI register access packet.

    Abstract translation: 本发明提供了一种数字数据接口设备消息格式，其描述了在具有系统控制器的数字设备和数字数据接口设备之间要交换的命令和响应消息。 数字数据接口设备包括消息解释器，内容模块和控制模块。 数字数据接口设备可以包括MDDI链路控制器。 数字数据接口设备可以被蜂窝电话用于控制诸如照相机，条形码读取器，图像扫描仪，音频设备或其他传感器的外围设备。 数字数据接口设备消息格式包括事务标识字段，计数字段，命令标识字段和状态字段。 可选地，消息格式可以包括数据字段。 当使用MDDI链路时，数字数据接口设备消息可以被包括在MDDI寄存器访问分组中。

    Systems and methods for implementing cyclic redundancy checks
    18.
    发明申请
    Systems and methods for implementing cyclic redundancy checks 失效
    用于实现循环冗余校验的系统和方法

    公开(公告)号：US20060168496A1

    公开(公告)日：2006-07-27

    申请号：US11285391

    申请日：2005-11-23

    Applicant: Brian Steele ,  George Wiley

    Inventor： Brian Steele ,  George Wiley

    IPC: H03M13/00

    CPC classification number: H04L1/0045 ,  H03M13/09 ,  H04L1/0061

    Abstract: The present invention provides systems and methods for implementing cyclic redundancy checks to improve link initialization processing and to exchange system error information. In one aspect, a cyclic redundancy check (CRC) checker is provided that includes a unique pattern detector, a CRC generator, a CRC initializer and a CRC verifier. The CRC checker prepopulates the CRC generator for a unique pattern. Upon receipt of the unique pattern within a data stream received over a digital transmission link, the CRC checker proceeds to check CRCs without the need to queue and store data. In another aspect, a CRC generator system is provided that intentionally corrupts CRC values to transmit system error information. The CRC generator system includes a CRC generator, a CRC corrupter, an error detector and an error value generator. In one example, the digital transmission link is an MDDI link.

    Abstract translation: 本发明提供了用于实现循环冗余检查以改善链路初始化处理和交换系统错误信息的系统和方法。 在一个方面，提供了包括唯一模式检测器，CRC发生器，CRC初始化器和CRC校验器的循环冗余校验（CRC）校验器。 CRC校验器预先为CRC生成器提供了一个独特的模式。 在接收到通过数字传输链路接收的数据流中的唯一模式之后，CRC检查器继续检查CRC，而不需要排队和存储数据。 在另一方面，提供了一种CRC发生器系统，其有意地破坏CRC值以传输系统错误信息。 CRC发生器系统包括CRC发生器，CRC腐蚀器，误差检测器和误差值发生器。 在一个示例中，数字传输链路是MDDI链路。

Patent Agency Ranking