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    Digital data interface device message format
    1.
    发明申请
    Digital data interface device message format 有权
    数字数据接口设备消息格式

    公开(公告)号：US20060179164A1

    公开(公告)日：2006-08-10

    申请号：US11285389

    申请日：2005-11-23

    Applicant: Behnam Katibian ,  George Wiley

    Inventor： Behnam Katibian ,  George Wiley

    IPC: G06F3/00

    CPC classification number: H04N21/43632 ,  H04M1/0214 ,  H04N21/41407 ,  H04N21/4223

    Abstract: The present invention provides a digital data interface device message format that describes command and response messages to be exchanged between a digital device having a system controller and a digital data interface device. The digital data interface device includes a message interpreter, content module and a control module. The digital data interface device may include an MDDI link controller. The digital data interface device can be used by a cellular telephone to control a peripheral device, such as a camera, bar code reader, image scanner, audio device or other sensor. The digital data interface device message format includes a transaction identification field, a count field, a command identification field and a status field. Optionally, the message format can include a data field. When an MDDI link is used, a digital data interface device message can be included in an MDDI register access packet.

    Abstract translation: 本发明提供了一种数字数据接口设备消息格式，其描述了在具有系统控制器的数字设备和数字数据接口设备之间要交换的命令和响应消息。 数字数据接口设备包括消息解释器，内容模块和控制模块。 数字数据接口设备可以包括MDDI链路控制器。 数字数据接口设备可以被蜂窝电话用于控制诸如照相机，条形码读取器，图像扫描仪，音频设备或其他传感器的外围设备。 数字数据接口设备消息格式包括事务标识字段，计数字段，命令标识字段和状态字段。 可选地，消息格式可以包括数据字段。 当使用MDDI链路时，数字数据接口设备消息可以被包括在MDDI寄存器访问分组中。

    Digital data interface device
    2.
    发明申请
    Digital data interface device 有权
    数字数据接口设备

    公开(公告)号：US20060288133A1

    公开(公告)日：2006-12-21

    申请号：US11285379

    申请日：2005-11-23

    Applicant: Behnam Katibian ,  George Wiley ,  Brian Steele

    Inventor： Behnam Katibian ,  George Wiley ,  Brian Steele

    IPC: G06F3/00

    CPC classification number: H04M1/7253

    Abstract: The present invention is directed a digital data interface device for transferring digital presentation data at a high rate over a communication link. The digital data interface device includes a message interpreter, content module and a control module. The digital data interface device may include an MDDI link controller. The digital data interface device can be used to control a peripheral device, such as a camera, bar code reader, image scanner, audio device or other sensor. In one example, a cellular telephone having a camera with an MDDI link and a digital data device interface is provided.

    Abstract translation: 本发明涉及一种用于通过通信链路以高速率传送数字呈现数据的数字数据接口设备。 数字数据接口设备包括消息解释器，内容模块和控制模块。 数字数据接口设备可以包括MDDI链路控制器。 数字数据接口设备可用于控制诸如照相机，条形码读取器，图像扫描器，音频设备或其他传感器的外围设备。 在一个示例中，提供具有具有MDDI链路的相机和数字数据设备接口的蜂窝电话。

    Methods and systems for synchronous execution of commands across a communication link
    4.
    发明申请
    Methods and systems for synchronous execution of commands across a communication link 审中-公开
    通过通信链路同步执行命令的方法和系统

    公开(公告)号：US20060161691A1

    公开(公告)日：2006-07-20

    申请号：US11285400

    申请日：2005-11-23

    Applicant: Behnam Katibian ,  George Wiley

    Inventor： Behnam Katibian ,  George Wiley

    IPC: G06F3/00

    CPC classification number: G03B17/00

    Abstract: A method for synchronously executing a plurality of commands generated by a first module and executed at a second module, wherein the first and second modules communicate through a communication link, is provided. The method includes generating the commands at the first module, transmitting the commands through the link to the second module, and associating the execution time of the commands with an independent event at the second module. When the independent event is detected, the commands are executed synchronously at the second module. The method can be specifically applied to a baseband processor controlling a camera through a camera interface module, wherein the processor and the camera interface module are connected through an MDDI link. An example of a baseband processor controlling a camera through a Pathfinder camera module interface module is described. Specific built-in mechanisms of the camera module interface that enable flexible implementation of the method are also provided.

    Abstract translation: 一种用于同步执行由第一模块生成并在第二模块执行的多个命令的方法，其中第一和第二模块通过通信链路进行通信。 该方法包括在第一模块处生成命令，通过链路将命令发送到第二模块，并将命令的执行时间与第二模块处的独立事件相关联。 当检测到独立事件时，在第二模块上同步执行命令。 该方法可以专门应用于通过摄像机接口模块控制摄像机的基带处理器，其中处理器和摄像机接口模块通过MDDI链路连接。 描述了通过Pathfinder相机模块接口模块控制相机的基带处理器的示例。 还提供了能够灵活实现该方法的相机模块接口的特定内置机制。

    Collapsible goal post for American football
    5.
    发明授权
    Collapsible goal post for American football 有权
    可折叠的美式足球目标职位

    公开(公告)号：US08496547B2

    公开(公告)日：2013-07-30

    申请号：US12958212

    申请日：2010-12-01

    Applicant: George Wiley

    Inventor： George Wiley

    IPC: A63B63/00

    CPC classification number: A63B63/008 ,  A63B2071/009 ,  A63B2210/50

    Abstract: A collapsible goal post includes a lower support extending from a playing field; a upper support having a first end and a second end, and a pivot assembly attaching the first end of the upper support to the lower support; an upper assembly comprising two uprights and a crossbar having two ends. The crossbar is attached to the second end of the support at about the midpoint of the crossbar. One of the two uprights is attached to each end of the crossbar. The upper support is configured to pivot about the pivot point assembly to move the upright assembly from a raised position to a lowered position. The two uprights are substantially perpendicular to the playing field in the raised position, and are substantially parallel to and contacting the playing field in the lowered position while the upper assembly and upper support remain attached to the lower support. In another embodiment, the goal post includes a hydraulic cylinder system coupled to the upper support and the lower support to hinder a rate of pivoting of the goal post about the pivot assembly.

    Abstract translation: 可折叠的目标岗位包括从游戏场延伸的较低支撑; 具有第一端和第二端的上支撑件和枢轴组件，所述枢轴组件将所述上支撑件的第一端附接到所述下支撑件; 包括两个立柱的上部组件和具有两个端部的横杆。 横杆在横杆的中点附近附接到支撑件的第二端。 两个立柱之一附在横梁的每一端。 上支撑件构造成围绕枢轴点组件枢转以将直立组件从升高位置移动到降低位置。 两个立柱基本上垂直于升高位置的运动场，并且在上部组件和上部支撑件保持附接到下部支撑件的同时基本上平行于并接触下降位置的运动场。 在另一个实施例中，目标柱包括联接到上支撑件和下支撑件的液压缸系统，以阻止球杆柱绕枢转组件枢转的速率。

    High data rate interface apparatus and method
    6.
    发明申请
    High data rate interface apparatus and method 有权

    公开(公告)号：US20060034326A1

    公开(公告)日：2006-02-16

    申请号：US11107536

    申请日：2005-04-14

    Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    IPC: H04J3/16

    CPC classification number: H04L69/22 ,  H04L69/18 ,  H04M1/72527 ,  Y02D70/144 ,  Y02D70/26

    Abstract: A data interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    Signal interface for higher data rates
    7.
    发明申请
    Signal interface for higher data rates 有权
    用于更高数据速率的信号接口

    公开(公告)号：US20050117601A1

    公开(公告)日：2005-06-02

    申请号：US10917930

    申请日：2004-08-12

    Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    IPC: G06F13/40 ,  H04L12/56 ,  H04L29/00 ,  H04L29/06 ,  H04M1/725

    CPC classification number: G06F13/4072 ,  H04L29/06027 ,  H04L65/607 ,  H04L69/22 ,  H04M1/72527 ,  Y02D70/00 ,  Y02D70/122 ,  Y02D70/1262 ,  Y02D70/144 ,  Y02D70/26

    Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

    DOUBLE DATA RATE SERIAL ENCODER
    10.
    发明申请
    DOUBLE DATA RATE SERIAL ENCODER 有权
    双数据速率串行编码器

    公开(公告)号：US20080088492A1

    公开(公告)日：2008-04-17

    申请号：US11937913

    申请日：2007-11-09

    Applicant: George Wiley ,  Brian Steele ,  Curtis Musfeldt

    Inventor： George Wiley ,  Brian Steele ,  Curtis Musfeldt

    IPC: H03M7/00

    CPC classification number: H03M7/16

    Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

    Abstract translation: 提供双数据速率串行编码器。 串行编码器包括具有多个输入的多路复用器，耦合到多路复用器的输入的多个锁存器，使得锁存器能够更新其数据输入的启动器，以及用于选择多路复用器的多个输入之一的计数器 用于输出。 在另一方面，多路复用器在输入转换期间提供无毛刺输出。 多路复用器包括基于由计数器提供的输入选择序列的先验知识而优化的输出选择算法。

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