公开(公告)号：US06518592B1

公开(公告)日：2003-02-11

申请号：US09713338

申请日：2000-11-16

申请人： Hiroyuki Amishiro ,  Kenji Yamaguchi

发明人： Hiroyuki Amishiro ,  Kenji Yamaguchi

IPC分类号： H01L2358

CPC分类号： G01R31/2621 ,  G01R27/02 ,  G01R31/2648 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

摘要： External resistance Rsd1 is obtained using a first evaluation pattern of MOSFETs having a gate contact length Lgc1 and a channel width W1 each (in steps 100 and 102). External resistance Rsd2 is then acquired by use of a second evaluation pattern of MOSFETs having a gate contact length Lgc2 and a channel with W2 each (in steps 100 and 104). Thereafter, sheet resistance Rsh and overlapping portion resistance Rdsw of the MOSFETs are computed (in step 106) in accordance with the following expressions: Rsh=(W2Rsd2−W1·Rsd1)/(Lgc2−Lgc1) Rdsw=(W1Lgc2·Rsd1−W2·Lgc1·Rsd2)/(Lgc2−Lgc1)

摘要翻译： 使用具有栅极接触长度Lgc1和沟道宽度W1的MOSFET的第一评估模式（步骤100和102）获得外部电阻Rsd1。 然后通过使用具有栅极接触长度Lgc2的MOSFET的第二评估模式和各自的沟道（步骤100和104）来获取外部电阻Rsd2。 此后，根据以下表达式计算MOSFET的薄层电阻Rsh和重叠部分电阻Rdsw（在步骤106中）：

公开(公告)号：US06468857B2

公开(公告)日：2002-10-22

申请号：US09927635

申请日：2001-08-13

申请人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

发明人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

IPC分类号： H01L218242

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823443 ,  H01L21/823475

摘要： Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.

摘要翻译： 提供一种半导体器件及其制造方法，其中将SAC结构的MOS晶体管和硅化物结构的MOS晶体管一起提供。 栅极结构（GT11〜GT13）的栅极电极（3）被上部氮化膜（4）和侧壁氮化物膜（5）覆盖。 因此，为了形成接触孔（CH1，CH2）选择性地除去作为氧化膜的层间绝缘膜（10），不会去除上部氮化物膜（4）和侧壁氮化物膜（5），能够防止栅电极 3）不被暴露。 特别地，在栅极结构（GT11和GT12）中，即使接触孔（CH1）位于任一侧，也不会在导体层（CL1）和栅电极（3）之间产生短路。 因此，栅极结构（GT11和GT12）可以被布置而不受接触孔（CH1）的对准边缘的限制，并且可以减小栅极之间的距离以获得高集成度。

公开(公告)号：US06445071B1

公开(公告)日：2002-09-03

申请号：US09488781

申请日：2000-01-21

申请人： Hideyo Haruhana ,  Hiroyuki Amishiro ,  Akihiko Harada

发明人： Hideyo Haruhana ,  Hiroyuki Amishiro ,  Akihiko Harada

IPC分类号： H01L2348

CPC分类号： H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, having a multi-layer interconnection structure, is provided which comprises a semiconductor substrate and a plurality of interlayer insulating films formed on the semiconductor substrate. A plurality of conductive leads are formed in the interlayer insulating films. In one of the interlayer insulting films having conductive lead or leads, at least one conductive plug is formed vertically to connect the conductive leads in different interlayer insulating films. Further, adjacent conductive leads may be formed in an adjacent interlayer insulating films are connected together to form a unified conductive lead.

摘要翻译： 提供具有多层互连结构的半导体器件，其包括形成在半导体衬底上的半导体衬底和多个层间绝缘膜。 在层间绝缘膜中形成多个导电引线。 在具有导电引线或引线的层间绝缘膜之一中，垂直形成至少一个导电插塞，以在不同的层间绝缘膜中连接导电引线。 此外，相邻的导电引线可以形成在相邻的层间绝缘膜中连接在一起以形成统一的导电引线。

公开(公告)号：US06288447B1

公开(公告)日：2001-09-11

申请号：US09353379

申请日：1999-07-15

申请人： Hiroyuki Amishiro ,  Motoshige Igarashi

发明人： Hiroyuki Amishiro ,  Motoshige Igarashi

IPC分类号： H01L2348

CPC分类号： H01L23/5283 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including an interconnection structure having superior electrical characteristics and allowing higher speed of operation and lower power consumption even when miniaturized, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method are provided. In the semiconductor device, a conductive region is formed on a main surface of a semiconductor substrate. A first interconnection layer is electrically connected to the conductive region, has a relatively short line length, and contains a material having relatively high electrical resistance. A first insulator is formed to surround the first interconnection layer and has a relatively low dielectric constant. A second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having low electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer. A second insulator is formed to surround the second interconnection layer and has a dielectric constant higher than the first insulator.

摘要翻译： 提供一种包括具有优异的电气特性并且即使当其小型化也允许更高的操作速度和更低的功率消耗的互连结构的半导体器件，并且提供了用于制造方法中使用的半导体电路的设计方法。 在半导体器件中，在半导体衬底的主表面上形成导电区域。 第一互连层电连接到导电区域，具有相对短的线路长度，并且包含具有相对较高电阻的材料。 形成第一绝缘体以包围第一互连层并且具有相对低的介电常数。 第二互连层形成在半导体衬底的主表面上，包含比第一互连层中包含的材料低的电阻，并且具有比第一互连层更长的线长度。 形成第二绝缘体以包围第二互连层并且具有高于第一绝缘体的介电常数。

公开(公告)号：US08089136B2

公开(公告)日：2012-01-03

申请号：US12891214

申请日：2010-09-27

申请人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

发明人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

IPC分类号： H01L29/00

CPC分类号： H01L27/0207 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20

摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

摘要翻译： 本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。 有源区靠近电阻元件配置。 这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

公开(公告)号：US20060175679A1

公开(公告)日：2006-08-10

申请号：US11384244

申请日：2006-03-21

申请人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

发明人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

IPC分类号： H01L29/00

CPC分类号： H01L27/0207 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20

摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

公开(公告)号：US07045865B2

公开(公告)日：2006-05-16

申请号：US09960495

申请日：2001-09-24

申请人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

发明人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

IPC分类号： H01L29/76 ,  H01L29/00 ,  H01L21/20

CPC分类号： H01L27/0207 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20

摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

摘要翻译： 本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。 有源区靠近电阻元件配置。 这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

公开(公告)号：US06838732B2

公开(公告)日：2005-01-04

申请号：US09971958

申请日：2001-10-09

申请人： Motoshige Igarashi ,  Hiroyuki Amishiro

发明人： Motoshige Igarashi ,  Hiroyuki Amishiro

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/088 ,  H01L27/11 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823468 ,  H01L23/5222 ,  H01L29/6653 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device with reduced parasitic capacity in the vicinity of gate electrodes, and a method for manufacturing such a semiconductor device. The semiconductor device comprises a gate electrode formed on a silicon semiconductor substrate 1 through a gate oxide film, and a pair of impurity diffusion layers formed on the surface region of the silicon semiconductor substrate at both sides of the gate electrode. A silicon nitride film acting as a sidewall spacer is formed so as to cover the sidewall of the gate electrode, and the silicon nitride film is allowed to extend to the surface of the silicon semiconductor substrate 1 in the vicinity of the gate electrode in a substantially L-shaped profile.

摘要翻译： 提供在栅极附近具有降低的寄生电容的半导体器件，以及制造这种半导体器件的方法。 半导体器件包括通过栅极氧化膜形成在硅半导体衬底1上的栅极电极和形成在栅极电极两侧的硅半导体衬底的表面区域上的一对杂质扩散层。 形成作为侧壁间隔物的氮化硅膜，以覆盖栅电极的侧壁，并且允许氮化硅膜基本上在栅电极附近延伸到硅半导体衬底1的表面 L型轮廓。

公开(公告)号：US06299314B1

公开(公告)日：2001-10-09

申请号：US09494785

申请日：2000-01-31

申请人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

发明人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823443 ,  H01L21/823475

摘要： Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of silicide structure are are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.

摘要翻译： 提供了一种半导体器件及其制造方法，其中将SAC结构的MOS晶体管和硅化物结构的MOS晶体管组合在一起。 栅极结构（GT11〜GT13）的栅极电极（3）被上部氮化膜（4）和侧壁氮化物膜（5）覆盖。 因此，为了形成接触孔（CH1，CH2）选择性地除去作为氧化膜的层间绝缘膜（10），不会去除上部氮化物膜（4）和侧壁氮化物膜（5），从而防止栅电极 3）不被暴露。 特别地，在栅极结构（GT11和GT12）中，即使接触孔（CH1）位于任一侧，也不会在导体层（CL1）和栅电极（3）之间产生短路。 因此，栅极结构（GT11和GT12）可以被布置而不受接触孔（CH1）的对准边缘的限制，并且可以减小栅极之间的距离以获得高集成度。

公开(公告)号：US5243560A

公开(公告)日：1993-09-07

申请号：US753571

申请日：1991-09-03

申请人： Hiroyuki Amishiro ,  Kumiko Fujimori

发明人： Hiroyuki Amishiro ,  Kumiko Fujimori

IPC分类号： G11C11/41 ,  G11C7/10

CPC分类号： G11C7/1006

摘要： The semiconductor memory device includes a memory cell array for storing a plurality of data on a word basis, a data input-output device and a read control device. The data input-output device includes a plurality of data holding circuits corresponding to one word. The data of one word is divided into a plurality of subwords. The read control device brings to an active state any one of a plurality of control signals corresponding to the plurality of subwords in response to an externally applied subword selection signal. The data holding circuit corresponding to one subword is thereby activated. As a result, any subword among the data of one word held in the data holding circuit is rewritten with a corresponding subword among the data of one word read from the memory cell array.

摘要翻译： 半导体存储器件包括用于以字为单位存储多个数据的存储单元阵列，数据输入输出设备和读控制器件。 数据输入输出装置包括对应于一个字的多个数据保持电路。 一个字的数据被分成多个子词。 读取控制装置响应于外部施加的子选择信号而使与多个子词对应的多个控制信号中的任何一个进入活动状态。 由此激活对应于一个子字的数据保持电路。 结果，在从存储单元阵列读出的一个字的数据中用对应的子字重写在数据保持电路中保存的一个字的数据中的任何一个子字。