公开(公告)号：US06303435B1

公开(公告)日：2001-10-16

申请号：US09531992

申请日：2000-03-20

Applicant: Horng-Nan Chern

Inventor： Horng-Nan Chern

IPC: H01L218242

CPC classification number: H01L28/60 ,  H01L21/76895 ,  H01L27/10855 ,  H01L28/84 ,  Y10S438/964

Abstract: A method of fabricating a wide-based boxed-structured capacitor containing hemi-spherical silicon grains. A substrate is provided with a source/drain and a first dielectric layer is formed on the substrate with a node contact opening. Then a doped polysilicon layer and a doped amorphous silicon layer are formed sequentially on the first dielectric layer. An etching step is performed to etch the doped amorphous silicon layer and the doped polysilicon layer and a wide-based lower electrode is formed by adjusting flow speeds of chlorine and of hydrogen bromide. Hemi-spherical silicon grains are formed on the surface of the doped amorphous silicon layer in the lower electrode. A second dielectric layer and an upper electrode are formed sequentially on the lower electrode and the capacitor is completed.

Abstract translation: 一种制造包含半球形硅晶粒的宽基盒装结构电容器的方法。 衬底设置有源极/漏极，并且第一介电层形成在具有节点接触开口的衬底上。 然后在第一介电层上依次形成掺杂多晶硅层和掺杂非晶硅层。 执行蚀刻步骤以蚀刻掺杂的非晶硅层和掺杂的多晶硅层，并且通过调节氯和溴化氢的流速来形成宽基底部电极。 在下电极中的掺杂非晶硅层的表面上形成半球形硅晶粒。 在下电极上依次形成第二电介质层和上电极，电容器完成。

公开(公告)号：US06211021B1

公开(公告)日：2001-04-03

申请号：US09360754

申请日：1999-07-26

Applicant: Chuan-Fu Wang ,  Horng-Nan Chern

Inventor： Chuan-Fu Wang ,  Horng-Nan Chern

IPC: H01L21336

CPC classification number: H01L21/76897 ,  H01L21/76237 ,  H01L21/823481

Abstract: A method of forming a borderless contact is described. An ion implantation process and a thermal process are performed on a device isolation structure to form a silicon nitride layer therein. During a process of forming a borderless contact window, the silicon nitride layer can serve as an etching stop layer to protect the device isolation structure from overetching. As a result, no recess is formed, and leakage current is avoided.

Abstract translation: 描述形成无边界接触的方法。 在器件隔离结构上进行离子注入工艺和热处理，以在其中形成氮化硅层。 在形成无边界接触窗的过程中，氮化硅层可以用作蚀刻停止层，以保护器件隔离结构不被过蚀刻。 结果，没有形成凹陷，并且避免了泄漏电流。

公开(公告)号：US06124161A

公开(公告)日：2000-09-26

申请号：US203022

申请日：1998-12-01

Applicant: Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

Inventor： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8234

CPC classification number: H01L28/84 ,  H01L27/10852

Abstract: A method for forming a hemispherical silicon grain (HSG) layer on a polysilicon electrode is provided. The method is suitable for a substrate, which has a dielectric layer over the substrate with an opening to expose the substrate, and a polysilicon layer is formed over the substrate. A portion of the polysilicon layer is removed above dielectric layer other than the opening region. Each sidewall of the polysilicon layer is slanted so that a trapezoidal polysilicon base is formed. A buffer layer is formed over the trapezoidal polysilicon base. An ion implantation process is performed to form an amorphous silicon layer with sufficient depth on a top surface region of the trapezoidal polysilicon base. The buffer layer includes silicon oxide or silicon nitride. During ion implantation, oxygen or nitrogen elements can also be bombarded into the amorphous silicon layer so as to buffer the amorphous silicon layer to be re-crystallized. A selective HSG layer is formed on the trapezoidal polysilicon electrode base.

Abstract translation: 提供了一种在多晶硅电极上形成半球形硅晶粒（HSG）层的方法。 该方法适合于在衬底上具有介电层的衬底，其具有用于暴露衬底的开口，并且在衬底上形成多晶硅层。 除了开口区域之外，在介电层上除去多晶硅层的一部分。 多晶硅层的每个侧壁都是倾斜的，从而形成梯形多晶硅基底。 缓冲层形成在梯形多晶硅基底上。 执行离子注入工艺以在梯形多晶硅基底的顶表面区域上形成具有足够深度的非晶硅层。 缓冲层包括氧化硅或氮化硅。 在离子注入期间，也可以将氧或氮元素轰击到非晶硅层中，以缓冲非晶硅层再结晶。 在梯形多晶硅电极基体上形成选择性HSG层。

公开(公告)号：US06403411B1

公开(公告)日：2002-06-11

申请号：US09208601

申请日：1998-12-08

Applicant: Chih-Hsun Chu ,  Horng-Nan Chern ,  Kevin Lin ,  Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

Inventor： Chih-Hsun Chu ,  Horng-Nan Chern ,  Kevin Lin ,  Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC: H01L218234

CPC classification number: H01L28/84 ,  H01L21/76895

Abstract: A method for manufacturing the lower electrode of a DRAM capacitor. The method includes depositing polysilicon instead of amorphous silicon to form the lower electrode. Because polysilicon has a higher depositing temperature, it has a higher depositing rate capable of shortening depositing time. After forming the polysilicon lower electrode, the upper portion of the polysilicon layer is transformed into an amorphous layer by bombarding the polysilicon layer with ions to damage its internal structure. Eventually, hemispherical grain silicon is able to grow over the lower electrode, thereby increasing its surface area.

Abstract translation: 一种用于制造DRAM电容器的下电极的方法。 该方法包括沉积多晶硅而不是非晶硅以形成下电极。 由于多晶硅具有较高的沉积温度，因此具有更高的沉积速率，能够缩短沉积时间。 在形成多晶硅下电极之后，通过用离子轰击多晶硅层将多晶硅层的上部转变成非晶层，以破坏其内部结构。 最终，半球形晶粒硅能够在下电极上生长，从而增加其表面积。

公开(公告)号：US06238974B1

公开(公告)日：2001-05-29

申请号：US09475212

申请日：1999-12-29

Applicant: Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

Inventor： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

IPC: H01L218242

CPC classification number: H01L28/84 ,  H01L21/76895 ,  H01L27/10852

Abstract: A process of fabricating a bottom electrode for the storage capacitors of DRAM is disclosed. The process includes first forming an insulation layer on the surface of the device substrate, with the insulation layer patterned to form a contact opening that exposes a source/drain region of the memory cell transistor. A first conductive layer then covers the insulation layer and fills into the contact opening, with the first conductive layer contacting the exposed source/drain region. A native oxide layer is then formed on the surface of the first conductive layer. A second electrically conductive layer is then formed and patterned to form a recess substantially above the location of the contact opening in the insulation layer. A layer of HSG—Si then covers the surface of the second conductive layer and the surface of the recess, and the HSG—Si layer and the second conductive layer are patterned to form the bottom electrode of the capacitor. The recess and its covering HSG—Si layer increase the effective surface area of the bottom electrode of the capacitor.

Abstract translation: 公开了制造用于DRAM的存储电容器的底部电极的工艺。 该方法包括首先在器件衬底的表面上形成绝缘层，其中图案化绝缘层以形成暴露存储单元晶体管的源/漏区的接触开口。 然后，第一导电层覆盖绝缘层并填充到接触开口中，第一导电层与暴露的源极/漏极区接触。 然后在第一导电层的表面上形成自然氧化物层。 然后形成第二导电层并图案化以形成基本上在绝缘层中的接触开口位置上方的凹部。 然后，HSG-Si层覆盖第二导电层的表面和凹部的表面，并且对HSG-Si层和第二导电层进行图案化以形成电容器的底部电极。 凹槽及其覆盖的HSG-Si层增加了电容器底部电极的有效表面积。

公开(公告)号：US06177310B1

公开(公告)日：2001-01-23

申请号：US09472132

申请日：1999-12-23

Applicant: Kuen-Yow Lin ,  Horng-Nan Chern

Inventor： Kuen-Yow Lin ,  Horng-Nan Chern

IPC: H01L218242

CPC classification number: H01L28/91 ,  H01L27/10852 ,  H01L28/84

Abstract: A method for forming a capacitor of memory cell is disclosed. The method includes, firstly, there is a semiconductor substrate that owns a first dielectric layer formed thereon. The first dielectric layer has a contact opening filled with doped polysilicon to form a stud. Then, a second dielectric layer is formed on the first dielectric layer and the surface of the stud. A silicon oxynitride (SiON) layer can be formed on the second dielectric layer. A photoresist layer is formed on the silicon oxynitride layer. Portions of the silicon oxynitride layer and the second dielectric layer are etched. Blanket and conformably forming an amorphous silicon layer is carried out. A third dielectric layer is formed on the amorphous silicon layer. The third dielectric layer and a portion of the amorphous silicon layer atop of the silicon oxynitride layer are all etched back. The silicon oxynitride layer is used as an anti-etching layer. The amorphous silicon layer will be treated to form a hemispherical-grained (HSG) layer on the surface of the amorphous silicon layer. The silicon oxynitride layer is removed. Dipping the surface of the second dielectric layer is achieved to comprehensively clean the surface thereof, thereby preventing unwanted connection of the hemispherical-grained layer on the capacitor with the hemispherical-grained layer out of the capacitor.

Abstract translation: 公开了一种形成存储单元的电容器的方法。 该方法首先包括在其上形成有第一电介质层的半导体衬底。 第一介电层具有填充有掺杂多晶硅的接触开口以形成螺柱。 然后，在第一电介质层和螺柱的表面上形成第二电介质层。 可以在第二介电层上形成氧氮化硅（SiON）层。 在氮氧化硅层上形成光致抗蚀剂层。 氧氮化硅层和第二电介质层的一部分被蚀刻。 进行毯子并顺应地形成非晶硅层。 在非晶硅层上形成第三电介质层。 第三电介质层和位于氧氮化硅层顶部的非晶硅层的一部分都被回蚀刻。 氧氮化硅层用作抗蚀刻层。 将非晶硅层处理以在非晶硅层的表面上形成半球形（HSG）层。 去除氧氮化硅层。 实现浸渍第二电介质层的表面以全面地清洁其表面，从而防止电容器上的半球形晶粒层与电容器的半球纹层不必要地连接。