公开(公告)号：US06124161A

公开(公告)日：2000-09-26

申请号：US203022

申请日：1998-12-01

申请人： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

发明人： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8234

CPC分类号： H01L28/84 ,  H01L27/10852

摘要： A method for forming a hemispherical silicon grain (HSG) layer on a polysilicon electrode is provided. The method is suitable for a substrate, which has a dielectric layer over the substrate with an opening to expose the substrate, and a polysilicon layer is formed over the substrate. A portion of the polysilicon layer is removed above dielectric layer other than the opening region. Each sidewall of the polysilicon layer is slanted so that a trapezoidal polysilicon base is formed. A buffer layer is formed over the trapezoidal polysilicon base. An ion implantation process is performed to form an amorphous silicon layer with sufficient depth on a top surface region of the trapezoidal polysilicon base. The buffer layer includes silicon oxide or silicon nitride. During ion implantation, oxygen or nitrogen elements can also be bombarded into the amorphous silicon layer so as to buffer the amorphous silicon layer to be re-crystallized. A selective HSG layer is formed on the trapezoidal polysilicon electrode base.

摘要翻译： 提供了一种在多晶硅电极上形成半球形硅晶粒（HSG）层的方法。 该方法适合于在衬底上具有介电层的衬底，其具有用于暴露衬底的开口，并且在衬底上形成多晶硅层。 除了开口区域之外，在介电层上除去多晶硅层的一部分。 多晶硅层的每个侧壁都是倾斜的，从而形成梯形多晶硅基底。 缓冲层形成在梯形多晶硅基底上。 执行离子注入工艺以在梯形多晶硅基底的顶表面区域上形成具有足够深度的非晶硅层。 缓冲层包括氧化硅或氮化硅。 在离子注入期间，也可以将氧或氮元素轰击到非晶硅层中，以缓冲非晶硅层再结晶。 在梯形多晶硅电极基体上形成选择性HSG层。

公开(公告)号：US06255229B1

公开(公告)日：2001-07-03

申请号：US09074780

申请日：1998-05-08

申请人： Kevin Lin ,  Horng-Nan Chern ,  Kun-Chi Lin

发明人： Kevin Lin ,  Horng-Nan Chern ,  Kun-Chi Lin

IPC分类号： H01L21469

CPC分类号： H01L21/0214 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/3145 ,  H01L21/31625 ,  H01L21/76801

摘要： A method for forming a semiconductor dielectric layer comprising the steps of providing a substrate having a plurality of semiconductor devices already formed thereon, and then forming a first dielectric layer over the substrate. Next, a silicon oxy-nitride layer is formed over the first dielectric layer, and finally a second dielectric layer is formed over the silicon oxy-nitride layer.

摘要翻译： 一种形成半导体电介质层的方法，包括以下步骤：提供其上已经形成有多个半导体器件的衬底，然后在衬底上形成第一电介质层。 接下来，在第一介电层上形成氮氧化硅层，最后在氮氧化硅层上形成第二电介质层。

公开(公告)号：US06238974B1

公开(公告)日：2001-05-29

申请号：US09475212

申请日：1999-12-29

申请人： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

发明人： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

IPC分类号： H01L218242

CPC分类号： H01L28/84 ,  H01L21/76895 ,  H01L27/10852

摘要： A process of fabricating a bottom electrode for the storage capacitors of DRAM is disclosed. The process includes first forming an insulation layer on the surface of the device substrate, with the insulation layer patterned to form a contact opening that exposes a source/drain region of the memory cell transistor. A first conductive layer then covers the insulation layer and fills into the contact opening, with the first conductive layer contacting the exposed source/drain region. A native oxide layer is then formed on the surface of the first conductive layer. A second electrically conductive layer is then formed and patterned to form a recess substantially above the location of the contact opening in the insulation layer. A layer of HSG—Si then covers the surface of the second conductive layer and the surface of the recess, and the HSG—Si layer and the second conductive layer are patterned to form the bottom electrode of the capacitor. The recess and its covering HSG—Si layer increase the effective surface area of the bottom electrode of the capacitor.

摘要翻译： 公开了制造用于DRAM的存储电容器的底部电极的工艺。 该方法包括首先在器件衬底的表面上形成绝缘层，其中图案化绝缘层以形成暴露存储单元晶体管的源/漏区的接触开口。 然后，第一导电层覆盖绝缘层并填充到接触开口中，第一导电层与暴露的源极/漏极区接触。 然后在第一导电层的表面上形成自然氧化物层。 然后形成第二导电层并图案化以形成基本上在绝缘层中的接触开口位置上方的凹部。 然后，HSG-Si层覆盖第二导电层的表面和凹部的表面，并且对HSG-Si层和第二导电层进行图案化以形成电容器的底部电极。 凹槽及其覆盖的HSG-Si层增加了电容器底部电极的有效表面积。

公开(公告)号：US6159806A

公开(公告)日：2000-12-12

申请号：US473985

申请日：1999-12-29

申请人： Horng-Nan Chern ,  Hsi-Chia Lin ,  Kun-Chi Lin

发明人： Horng-Nan Chern ,  Hsi-Chia Lin ,  Kun-Chi Lin

IPC分类号： H01L21/8234

CPC分类号： H01L21/823468

摘要： A method for depositing an oxide layer after spacer formation is disclosed. Owing to an oxide layer after spacer formation, therefore substantially increasing the effective thickness of spacer of the peripheral circuit. The method includes which includes a substrate on which an interior and a peripheral circuit are defined, wherein there is a gate oxide layer formed on the substrate. Sequentially an interior gate and a peripheral gate are formed. Then, N-type ions are implanted into the substrate of the interior and peripheral circuit. Consequently, conformal a second dielectric layer and a third dielectric layer are deposited above the substrate, interior gate, and peripheral gate, wherein second dielectric layer is etched to form a spacer of the interior gate and the peripheral gate. And then N.sup.+ -type ions are implanted into the substrate to form source/drain by using the peripheral gate, the spacer and a portion of the third dielectric layer that runs along the spacer as a mask. Subsequently, a blanket inter-plasma dielectric is deposited above the substrate. Finally, inter-polysilicon dielectric of the interior and peripheral circuit is etched anisotropically to form a plurality of contacts.

摘要翻译： 公开了一种在间隔物形成之后沉积氧化物层的方法。 由于在间隔物形成之后的氧化物层，因此大大增加了外围电路的间隔物的有效厚度。 该方法包括其中限定了内部和外围电路的衬底，其中在衬底上形成有栅极氧化层。 顺序地形成内部门和外围门。 然后，将N型离子注入到内部和外围电路的衬底中。 因此，在衬底，内部栅极和外围栅极上方沉积第二绝缘层和第三介电层，其中第二介电层被蚀刻以形成内部栅极和外围栅极的间隔物。 然后通过使用外围栅极，间隔物和沿着间隔物延伸作为掩模的第三电介质层的一部分，将N +型离子注入到衬底中以形成源极/漏极。 随后，在衬底上方沉积一层等离子体电介质。 最后，各向异性地蚀刻内部和外围电路的多晶硅间电介质以形成多个触点。

公开(公告)号：US6100158A

公开(公告)日：2000-08-08

申请号：US302884

申请日：1999-04-30

申请人： Tzung-Han Lee ,  Kun-Chi Lin ,  Horng-Nan Chern ,  Alex Hou

发明人： Tzung-Han Lee ,  Kun-Chi Lin ,  Horng-Nan Chern ,  Alex Hou

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method of manufacturing an alignment mark. A substrate having a device region and an alignment mark region is provided. The device region is higher than the alignment mark region. The device region comprises an active region. An isolation structure is formed in the substrate at the edge of the alignment mark region and a first dielectric layer is formed over a portion of the substrate at the alignment mark region, simultaneously. A conductive layer is formed over the substrate. A portion of the conductive layer is removed to expose the first dielectric layer at the alignment mark region. The remaining conductive layer is patterned to form a component at the active region. A second dielectric layer with a smooth surface is formed over the substrate to cover the component. A wire is formed on the second dielectric layer, wherein a distance between the wire and the alignment mark region is larger than a distance between the component and the alignment mark region.

摘要翻译： 制造对准标记的方法。 提供具有器件区域和对准标记区域的衬底。 器件区域高于对准标记区域。 器件区域包括有源区。 在对准标记区域的边缘处的基板中形成隔离结构，同时在对准标记区域的一部分基板上形成第一电介质层。 导电层形成在衬底上。 去除导电层的一部分以在对准标记区域露出第一介电层。 将剩余的导电层图案化以在有源区域形成部件。 在衬底上形成具有光滑表面的第二电介质层以覆盖该部件。 在第二电介质层上形成导线，其中导线与对准标记区域之间的距离大于部件与对准标记区域之间的距离。

公开(公告)号：US06429135B1

公开(公告)日：2002-08-06

申请号：US09754354

申请日：2001-01-05

申请人： Horng-Nan Chern ,  Kun-Chi Lin

发明人： Horng-Nan Chern ,  Kun-Chi Lin

IPC分类号： H01L21302

CPC分类号： H01L21/823425 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823468

摘要： The semiconductor wafer includes a substrate, a gate positioned on the substrate, a cap layer positioned on top of the gate, and a silicon oxide spacer positioned around both the gate and the cap layer. Firstly, a dielectric layer is formed on the semiconductor wafer to cover the gate. An etching back process is then performed to remove portions of both the dielectric layer and the silicon oxide spacer. Finally, a silicon nitride spacer is formed on the dielectric layer around the cap layer. The silicon nitride spacer is positioned on the surface of the dielectric layer and functions in reducing stress between the silicon nitride spacer and the substrate.

摘要翻译： 半导体晶片包括衬底，位于衬底上的栅极，位于栅极顶部的覆盖层和位于栅极和盖层两侧的氧化硅间隔物。 首先，在半导体晶片上形成介电层以覆盖栅极。 然后进行蚀刻反应处理以去除电介质层和氧化硅间隔物的部分。 最后，在覆盖层周围的电介质层上形成氮化硅间隔物。 氮化硅间隔物定位在电介质层的表面上，起减少氮化硅间隔物和衬底之间的应力的作用。

公开(公告)号：US6140202A

公开(公告)日：2000-10-31

申请号：US208739

申请日：1998-12-08

申请人： Horng-Nan Chern ,  Kun-Chi Lin

发明人： Horng-Nan Chern ,  Kun-Chi Lin

IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/8242

CPC分类号： H01L28/92 ,  H01L21/32139 ,  H01L27/10852

摘要： A method for fabricating a double-cylinder capacitor is provided. The double-cylinder capacitor has a storage electrode having dual, concentric cylinder structures. The dielectric layer and the top electrode are formed in sequence over the bottom electrode. The storage area is thus enlarged by the double-cylinder capacitor of the invention. Thus, the capacitance of the capacitor can be effectively increased.

摘要翻译： 提供一种制造双缸电容器的方法。 双缸电容器具有具有双重同心圆筒结构的存储电极。 电介质层和顶电极依次形成在底电极上。 因此，通过本发明的双缸电容器来扩大存储区域。 因此，可以有效地增加电容器的电容。

公开(公告)号：US6150263A

公开(公告)日：2000-11-21

申请号：US188920

申请日：1998-11-09

申请人： Kevin Lin ,  Ching-Chiao Hao ,  Kun-Chi Lin

发明人： Kevin Lin ,  Ching-Chiao Hao ,  Kun-Chi Lin

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76885

摘要： A method of forming small dimension wires by an isotropic removal process. The method provides a substrate with an insulation layer. A first conductive layer and a second conductive layer are formed on the insulation layer. A wire pattern is formed on a photoresist layer after the coating process and the sequential exposure and development process. Part of the second conductive layer is removed by using the wire pattern on the photoresist layer as a mask, and thus part of the second conductive layer with wires is remained. Isotropic etching the peripheral part of the second conductive layer and thus the part of wire pattern with a smaller dimension is remained. Using the wire pattern with a smaller dimension as a mask to anisotropic etch the first conductive layer until the surface of the insulation layer is exposed, and thus the process of fabricating small dimension is finished.

摘要翻译： 通过各向同性去除方法形成小尺寸线的方法。 该方法提供具有绝缘层的基板。 第一导电层和第二导电层形成在绝缘层上。 在涂布工艺和顺序曝光和显影处理之后，在光致抗蚀剂层上形成线图案。 通过使用光致抗蚀剂层上的线图案作为掩模来去除部分第二导电层，因此残留了具有导线的第二导电层的一部分。 残留了各向同性蚀刻第二导电层的周边部分，因此保留了具有较小尺寸的线图案的部分。 使用较小尺寸的导线图案作为掩模以对第一导电层进行各向异性蚀刻，直到绝缘层的表面露出，从而完成制造小尺寸的工艺。

公开(公告)号：US6074955A

公开(公告)日：2000-06-13

申请号：US189116

申请日：1998-11-09

申请人： Kevin Lin ,  Chia-Wen Liang ,  Kun-Chi Lin

发明人： Kevin Lin ,  Chia-Wen Liang ,  Kun-Chi Lin

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/31144 ,  H01L27/10873 ,  H01L27/10882

摘要： A method of fabricating a node contact window. A substrate having devices and a first dielectric layer is provided. Bit lines having spacer are formed on the first dielectric layer and a second is formed on the first dielectric layer. A hard material layer is then formed on the second dielectric layer. An opening is formed within the second dielectric layer to expose the spacer and the first dielectric layer. A polysilicon spacer is then formed on the sidewalls of the opening. A node contact window is formed by etching through the first dielectric layer to expose the substrate.

摘要翻译： 一种制造节点接触窗口的方法。 提供具有器件和第一介电层的衬底。 具有间隔物的位线形成在第一电介质层上，第二电极形成在第一电介质层上。 然后在第二电介质层上形成硬质材料层。 在第二电介质层内形成开口以露出间隔物和第一介电层。 然后在开口的侧壁上形成多晶硅间隔物。 通过蚀刻穿过第一电介质层形成节点接触窗，露出衬底。

公开(公告)号：US6162678A

公开(公告)日：2000-12-19

申请号：US188916

申请日：1998-11-09

申请人： Kevin Lin ,  Ching-Chiao Hao ,  Kun-Chi Lin

发明人： Kevin Lin ,  Ching-Chiao Hao ,  Kun-Chi Lin

IPC分类号： H01L21/768 ,  H01L21/8242

CPC分类号： H01L21/76885 ,  H01L21/76888 ,  H01L27/10885

摘要： A method for fabricating a type of bit line is able to form a small-sized bit line. In this method a first dielectric layer, a first conductive layer, and a second conductive layer are formed on a substrate in sequence. The first dielectric layer is exposed, then a second conducting wire and a first conducting wire are formed, respectively. A portion of the second conducting wire is removed by a cleaning liquid, so that the feature size of the second conducting wire is less than the feature size of the first conducting wire. An oxide layer is formed on the second conducting wire and the first conducting wire by performing a thermal treatment. The feature size of the second conducting wire is approximately equal to the feature size of the first conducting wire.

摘要翻译： 一种用于制造位线的方法能够形成小尺寸的位线。 在该方法中，依次在基板上形成第一电介质层，第一导电层和第二导电层。 第一介质层被暴露，然后分别形成第二导线和第一导线。 第二导线的一部分被清洁液体除去，使得第二导线的特征尺寸小于第一导线的特征尺寸。 通过进行热处理，在第二导线和第一导线上形成氧化物层。 第二导线的特征尺寸近似等于第一导线的特征尺寸。