公开(公告)号：US20070037355A1

公开(公告)日：2007-02-15

申请号：US11438603

申请日：2006-05-22

Applicant: Jian-Hsing Lee ,  Yu-Chang Jong

Inventor： Jian-Hsing Lee ,  Yu-Chang Jong

IPC: H01L21/331

CPC classification number: H01L27/0259

Abstract: An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

Abstract translation: 提供一种静电放电（ESD）保护结构及其形成方法。 该结构包括具有掩埋层的衬底以及掩埋层上的第一和第二高压阱区。 第一和第二高电压阱区具有相反的导电类型并且物理上彼此接触。 该结构还包括从第一高电压阱区域延伸到第二高电压阱区域的场区域，第一高压阱区域中的第一掺杂区域和与场区域物理接触的第二掺杂区域， 第二高压井区域并物理接触场区域。 第一和第二掺杂区域和第一高电压阱区域形成可以保护集成电路免受ESD的双极晶体管。

公开(公告)号：US20070034956A1

公开(公告)日：2007-02-15

申请号：US11199662

申请日：2005-08-09

Applicant: Jian-Hsing Lee ,  Yu-Chang Jong

Inventor： Jian-Hsing Lee ,  Yu-Chang Jong

IPC: H01L23/62

CPC classification number: H01L29/7393 ,  H01L27/0262 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/7436

Abstract: A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain region doped with a p-type impurity in a high voltage p-well (HVPW) region, a second source/drain region doped with a p-type impurity in a high voltage n-well (HVNW) region wherein the HVPW region and HVNW region physically contact each other, a field region substantially underlying a gate dielectric, and a first heavily doped n-type (N+) region in the HVPW region and contacting the first source/drain region. The device further includes an N+ buried layer underlying the HVPW region and the HVNW region and a p-type substrate underlying the N+ buried layer. The device has robust performance for both forward and reverse mode ESD.

Abstract translation: 提供了具有静电放电（ESD）保护功能的高电压p型金属氧化物半导体（HVPMOS）器件及其形成方法。 HVPMOS包括PMOS晶体管，其中PMOS晶体管包括在高压p阱（HVPW）区域中掺杂有p型杂质的第一源极/漏极区域，掺杂有p型杂质的第二源极/漏极区域 在HVPW区域和HVNW区域彼此物理接触的场合，HVPW区域中基本上位于栅极电介质的场区域和第一重掺杂n型（N +）区域的高电压n阱（HVNW）区域中， 第一源极/漏极区域。 该器件还包括位于HVPW区域和HVNW区域下面的N +掩埋层和位于N +掩埋层下面的p型衬底。 该器件具有强大的正向和反向模式ESD性能。

公开(公告)号：US07148574B2

公开(公告)日：2006-12-12

申请号：US10824035

申请日：2004-04-14

Applicant: Jian-Hsing Lee ,  Pao-Kang Niu ,  Ko-Yi Lee

Inventor： Jian-Hsing Lee ,  Pao-Kang Niu ,  Ko-Yi Lee

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/60 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05138 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2224/45099

Abstract: A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edge portion, a second conductive layer having a wire bonding portion and a second edge portion and a plurality of plugs electrically connecting the wiring layer and the wire bonding portion. A conductive structure of an array of metal plugs or a metal damascene structure is formed to connect the first edge portion and the second edge portion, thereby preventing burn out of the first edge portion during an ESD event.

Abstract translation: 一种焊盘结构及其制造方法。 接合焊盘基本上由电介质层包围和绝缘，其中焊盘由至少一个第一导电层形成，第一导电层具有带状布局的布线层和第一边缘部分，第二导电层具有引线接合部分， 第二边缘部分和电连接所述布线层和所述引线接合部分的多个插塞。 形成金属插塞或金属镶嵌结构阵列的导电结构以连接第一边缘部分和第二边缘部分，从而防止在ESD事件期间烧坏第一边缘部分。

公开(公告)号：US20060274465A1

公开(公告)日：2006-12-07

申请号：US11140991

申请日：2005-06-01

Applicant: Chau-Neng Wu ,  Jian-Hsing Lee

Inventor： Chau-Neng Wu ,  Jian-Hsing Lee

IPC: H02H9/00

CPC classification number: H01L27/0251

Abstract: An electrostatic discharge (ESD) protection circuit is provided for use in an integrated circuit (IC) to provide protection against an ESD on a contact pad of the IC. The IC includes a driver circuit. The ESD protection circuit is connectable to a first power supply voltage and includes an ESD protection device connectable between the contact pad and the first power supply voltage and a capacitor connectable between the contact pad and the driver circuit.

Abstract translation: 提供了用于集成电路（IC）中的静电放电（ESD）保护电路，以提供针对IC接触焊盘上ESD的保护。 IC包括驱动电路。 ESD保护电路可连接到第一电源电压，并且包括可在接触焊盘和第一电源电压之间连接的ESD保护装置以及可在接触焊盘和驱动器电路之间连接的电容器。

公开(公告)号：US20060234399A1

公开(公告)日：2006-10-19

申请号：US11107068

申请日：2005-04-15

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee

IPC: H01L21/00

CPC classification number: H01L27/0288

Abstract: A method is disclosed for enhancing ESD protection of integrated circuit devices. The method entails placing a resistor between an I/O pad and an ESD protection device on a semiconductor chip so that one end of the resistor connects to pins on said I/O pad and the other end connects to the ESD protection device.

Abstract translation: 公开了一种用于增强集成电路器件的ESD保护的方法。 该方法需要在半导体芯片上的I / O焊盘和ESD保护器件之间放置电阻器，使得电阻器的一端连接到所述I / O焊盘上的引脚，另一端连接到ESD保护器件。

公开(公告)号：US20060192251A1

公开(公告)日：2006-08-31

申请号：US11065848

申请日：2005-02-25

Applicant: Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Yang

Inventor： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Yang

IPC: H01L23/62

CPC classification number: H01L29/7436 ,  H01L29/74

Abstract: A system and method is disclosed for implementing a new bipolar-based silicon controlled rectifier (SCR) circuit for an electrostatic discharge (ESD) protection. The SCR circuit comprises a bipolar device to be formed on a semiconductor substrate. The bipolar device comprises at least an N-well for providing a high resistance and a P+ material to be used as a collector thereof for further providing a high resistance. At least an Nmoat guard ring and a Pmoat guard ring surround the bipolar device, wherein when an ESD event occurs, the high resistance provided by the N-well and the P+ material of the bipolar device increases a turn-on speed.

Abstract translation: 公开了一种用于实现用于静电放电（ESD）保护的新的基于双极的可控硅整流器（SCR）电路的系统和方法。 SCR电路包括要形成在半导体衬底上的双极器件。 双极器件至少包括用于提供高电阻的N阱和用作集电极的P +材料以进一步提供高电阻。 至少一个Nmoat保护环和Pmoat保护环围绕双极器件，其中当ESD事件发生时，由N阱和双极器件的P +材料提供的高电阻增加了接通速度。

公开(公告)号：US07078772B2

公开(公告)日：2006-07-18

申请号：US10820320

申请日：2004-06-08

Applicant: Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01L23/62

CPC classification number: H01L27/0292 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

Abstract translation: 本发明提供了用于整个芯片静电放电，ECD，保护方案的两个电路实施例。 它还包括一种全芯片ESD保护方法。 本发明涉及将本发明的电路分配给每个输入/输出焊盘，以便提供并联的ESD电流放电路径。 本发明的优点是能够快速地形成对地的平行放电路径，以便有效地放电损坏的ESD电流，以避免电路损坏。 两个电路实施例示出了本发明的保护电路如何在未分离的I / O焊盘和已加热的I / O焊盘两端均以并联电路连接，以快速放电ESD电流。 这些保护实施例需要少量的半导体区域，因为较小的保护电路分布并放置在每个I / O焊盘的位置。

公开(公告)号：US20060097330A1

公开(公告)日：2006-05-11

申请号：US10985532

申请日：2004-11-10

Applicant: Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Yang

Inventor： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Yang

IPC: H01L29/76

CPC classification number: H01L21/76816 ,  H01L27/0274 ,  H01L29/78

Abstract: A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.

公开(公告)号：US20050230847A1

公开(公告)日：2005-10-20

申请号：US10824035

申请日：2004-04-14

Applicant: Jian-Hsing Lee ,  Pao-Kang Niu ,  Ko-Yi Lee

Inventor： Jian-Hsing Lee ,  Pao-Kang Niu ,  Ko-Yi Lee

IPC: H01L23/48 ,  H01L23/485 ,  H01L23/60

CPC classification number: H01L24/05 ,  H01L23/60 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05138 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2224/45099

Abstract: A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edge portion, a second conductive layer having a wire bonding portion and a second edge portion and a plurality of plugs electrically connecting the wiring layer and the wire bonding portion. A conductive structure of an array of metal plugs or a metal damascene structure is formed to connect the first edge portion and the second edge portion, thereby preventing burn out of the first edge portion during an ESD event.

Abstract translation: 一种焊盘结构及其制造方法。 焊盘基本上由电介质层包围和绝缘，其中焊盘由具有带状布局的布线层和第一边缘部分的至少一个第一导电层形成，第二导电层具有引线接合部分， 第二边缘部分和电连接所述布线层和所述引线接合部分的多个插塞。 形成金属插塞或金属镶嵌结构阵列的导电结构以连接第一边缘部分和第二边缘部分，从而防止在ESD事件期间烧坏第一边缘部分。

公开(公告)号：US06937457B2

公开(公告)日：2005-08-30

申请号：US10694129

申请日：2003-10-27

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01G4/228 ,  H01G4/35 ,  H01L21/8234 ,  H01L23/60 ,  H02H9/00

CPC classification number: H01L27/0251

Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.

Abstract translation: 在集成电路（IC）上提供了具有增加的静电放电阻抗（ESD）的去耦电容器。 电容器可以是单指或多指。 在一个示例中，电容器包括由电介质材料隔开的第一和第二电极，靠近第一电极定位的源，以及靠近第一电极定位并与第一电极分离的浮动漏极。 通过源极，浮置漏极和掺杂区域之间的电流相互作用形成了被建模为双极结型晶体管（BJT）的寄生元件。 浮动漏极在BJT的基极处提供恒定的电位区域，从而最大程度降低对IC的ESD损坏。