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    Integrated circuits using guard rings for ESD, systems, and methods for forming the integrated circuits
    5.
    发明授权
    Integrated circuits using guard rings for ESD, systems, and methods for forming the integrated circuits 有权
    使用ESD保护环的集成电路，系统和用于形成集成电路的方法

    公开(公告)号：US08344416B2

    公开(公告)日：2013-01-01

    申请号：US12777672

    申请日：2010-05-11

    申请人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

    发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

    IPC分类号： H01L29/02

    CPC分类号： H01L27/0251 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7835

    摘要： An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

    摘要翻译： 集成电路在衬底上包括至少一个晶体管。 第一保护环布置在至少一个晶体管周围。 第一保护环具有第一类型掺杂剂。 第二保护环设置在第一保护环周围。 第二保护环具有第二类型掺杂剂。 第一掺杂区域邻近第一保护环设置。 第一掺杂区具有第二类掺杂剂。 第二掺杂区域邻近第二保护环设置。 第二掺杂区具有第一类掺杂剂。 第一保护环，第二保护环，第一掺杂区和第二掺杂区能够用作第一可控硅整流器（SCR），以基本上释放静电放电（ESD）。

    ESD protection structures on SOI substrates
    6.
    发明授权
    ESD protection structures on SOI substrates 有权
    SOI衬底上的ESD保护结构

    公开(公告)号：US08288822B2

    公开(公告)日：2012-10-16

    申请号：US13172555

    申请日：2011-06-29

    申请人： Jiaw-Ren Shih ,  Jian-Hsing Lee

    发明人： Jiaw-Ren Shih ,  Jian-Hsing Lee

    IPC分类号： H01L27/06

    CPC分类号： H01L27/0259 ,  H01L27/1203

    摘要： An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

    摘要翻译： 静电放电（ESD）保护电路包括埋氧层; 掩埋氧化物层上的半导体层; 以及第一和第二MOS器件。 第一MOS器件包括半导体层上的第一栅极; 第一阱区，具有位于第一栅极下面的部分; 以及半导体层中的第一源极区域和第一漏极区域。 第二MOS器件包括半导体层上的第二栅极; 以及具有位于第一栅极下方的部分的第二阱区。 第二阱区连接到放电节点。 第一阱区域通过第二阱区域连接到放电节点，并且不直接连接到放电节点。 第二MOS器件还包括半导体层中的第二源极区域和第二漏极区域并与第二阱区域邻接。

    ESD Protection Structures on SOI Substrates
    7.
    发明申请
    ESD Protection Structures on SOI Substrates 有权
    SOI衬底上的ESD保护结构

    公开(公告)号：US20110254091A1

    公开(公告)日：2011-10-20

    申请号：US13172555

    申请日：2011-06-29

    申请人： Jiaw-Ren Shih ,  Jian-Hsing Lee

    发明人： Jiaw-Ren Shih ,  Jian-Hsing Lee

    IPC分类号： H01L27/12

    CPC分类号： H01L27/0259 ,  H01L27/1203

    摘要： An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

    摘要翻译： 静电放电（ESD）保护电路包括埋氧层; 掩埋氧化物层上的半导体层; 以及第一和第二MOS器件。 第一MOS器件包括半导体层上的第一栅极; 第一阱区，具有位于第一栅极下面的部分; 以及半导体层中的第一源极区域和第一漏极区域。 第二MOS器件包括半导体层上的第二栅极; 以及具有位于第一栅极下方的部分的第二阱区。 第二阱区连接到放电节点。 第一阱区域通过第二阱区域连接到放电节点，并且不直接连接到放电节点。 第二MOS器件还包括半导体层中的第二源极区域和第二漏极区域并与第二阱区域邻接。

    NOVEL METHOD FOR FOUR DIRECTION LOW CAPACITANCE ESD PROTECTION
    8.
    发明申请
    NOVEL METHOD FOR FOUR DIRECTION LOW CAPACITANCE ESD PROTECTION 有权
    四方向低电容ESD保护的新方法

    公开(公告)号：US20090101937A1

    公开(公告)日：2009-04-23

    申请号：US12342294

    申请日：2008-12-23

    申请人： Jian-Hsing Lee ,  Shui-Hunyi Chen

    发明人： Jian-Hsing Lee ,  Shui-Hunyi Chen

    IPC分类号： H01L29/73

    CPC分类号： H01L27/0255

    摘要： The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

    摘要翻译： 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由围绕I / O ESD保护器件和Vcc至Bss保护器件的重掺杂P +保护环组成。 另外，在I / O保护器件的P +保护环周围还有一个重掺杂的N +保护环。 保护环增强结构二极管元件，提供增强的ESD能量放电路径能力，从而能够消除特定的常规Vss至I / O焊盘ESD保护器件。 这降低了I / O电路所看到的电容，同时为有源电路器件提供足够的ESD保护。

    Electrostatic discharge protection device having light doped regions
    9.
    发明授权
    Electrostatic discharge protection device having light doped regions 有权
    具有轻掺杂区域的静电放电保护器件

    公开(公告)号：US07420250B2

    公开(公告)日：2008-09-02

    申请号：US11212000

    申请日：2005-08-25

    申请人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

    发明人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0255

    摘要： Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.

    摘要翻译： 提供一种静电放电（ESD）保护装置及其制造方法。 在一个示例中，ESD保护装置包括形成在衬底中的齐纳二极管区域和邻近齐纳二极管区域形成的N型金属氧化物半导体（NMOS）器件。 齐纳二极管区域具有两个掺杂区域，位于两个掺杂区域之间的接地电位的栅极和在衬底中形成的两个光掺杂漏极（LDD）特征。 LDD特征之一位于两个掺杂区域和栅极之间。 NMOS器件包括形成在衬底中的源极和漏极，以及位于源极和漏极之间的第二栅极。

    ESD protection scheme for semiconductor devices having dummy pads
    10.
    发明申请
    ESD protection scheme for semiconductor devices having dummy pads 审中-公开

    公开(公告)号：US20080174923A1

    公开(公告)日：2008-07-24

    申请号：US11812221

    申请日：2007-06-15

    申请人： Yi-Hsun Wu ,  Yan-Chih Jiang ,  Yu-Chang Lin ,  Jian-Hsing Lee

    发明人： Yi-Hsun Wu ,  Yan-Chih Jiang ,  Yu-Chang Lin ,  Jian-Hsing Lee

    IPC分类号： H02H9/00 ,  H01L21/336

    CPC分类号： H01L27/0255

    摘要： A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; and a dummy pad formed over the plurality of layers of metal lines, the dummy pad having a diode connected thereto and to ground for providing a discharge path for the electrostatic discharge and/or accumulated charge.