公开(公告)号：US20110175769A1

公开(公告)日：2011-07-21

申请号：US12910314

申请日：2010-10-22

Applicant: Jae Jin Lee ,  Chung Hwan Kim ,  Min Gun Kim

Inventor： Jae Jin Lee ,  Chung Hwan Kim ,  Min Gun Kim

IPC: G01S13/00

CPC classification number: G01S7/034 ,  H01Q1/48 ,  H01Q9/30 ,  H01Q13/00

Abstract: Microwave sensor includes an oscillator for generating microwave signals, a power divider for dividing the microwave signals, an antenna for transmitting the divided microwave signals to an outside of the microwave sensor and receiving microwave signals reflected from an object, and a mixer for detecting differences between the microwave signals received through the antenna and the signals input from the power divider and outputting Intermediate Frequency (IF) signals. The antenna includes a ground plate, an antenna pin located at a center of the ground plate, and a metallic wall formed along a circumference of the ground plate. Accordingly, the microwave sensor is advantageous in that it has uniform gain characteristics regardless of an azimuth angle by using a single antenna, functioning as both transmitting and receiving antennas, and a circuit for operating the antenna.

Abstract translation: 微波传感器包括用于产生微波信号的振荡器，用于分割微波信号的功率分配器，用于将分离的微波信号传输到微波传感器的外部并接收从对象反射的微波信号的天线，以及用于检测 通过天线接收的微波信号和从功率分配器输入的信号并输出​​中频（IF）信号。 天线包括接地板，位于接地板中心的天线针脚和沿着接地板的圆周形成的金属壁。 因此，微波传感器的优点在于，通过使用用作发射和接收天线两者的单个天线以及用于操作天线的电路，其具有均匀的增益特性，而不管方位角如何。

公开(公告)号：US20110158026A1

公开(公告)日：2011-06-30

申请号：US12835978

申请日：2010-07-14

Applicant: Jin Youp CHA ,  Jae Jin Lee

Inventor： Jin Youp CHA ,  Jae Jin Lee

IPC: G11C17/16

CPC classification number: G11C17/16 ,  G11C29/785

Abstract: A fuse circuit includes a plurality of fuse sets configured to perform fuse programming and generate fuse signals in response to fuse programming signals and a fuse control unit configured to generate the fuse programming signals depending upon a level of a programming voltage.

Abstract translation: 熔丝电路包括配置成执行熔丝编程并响应于熔丝编程信号产生熔丝信号的多个熔丝组，以及配置成根据编程电压的电平产生熔丝编程信号的熔丝控制单元。

公开(公告)号：US20110116550A1

公开(公告)日：2011-05-19

申请号：US12837022

申请日：2010-07-15

Applicant: Jae Jin Lee ,  Moo Kyoung Chung ,  Kyung Su Kim ,  Jun Young Lee ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Jae Jin Lee ,  Moo Kyoung Chung ,  Kyung Su Kim ,  Jun Young Lee ,  Seong Mo Park ,  Nak Woong Eum

IPC: H04N11/02

CPC classification number: H04N19/436 ,  H04N19/44 ,  H04N19/61

Abstract: A video decoding apparatus and method based on a data and function splitting scheme are disclosed. The video decoding apparatus based on a data and function splitting scheme includes a variable length decoding unit performing variable length decoding and parsing on a bit stream to acquire residual data and a decoding parameter, and splitting the residual data and the decoding parameter by row; and N (N is a natural number of 2 or larger) number of clusters splitting dequantization and inverse discrete cosine transform (IDCT), motion vector prediction, intra prediction and motion compensation, video restoration, and deblocking function into M number of functions, acquiring the residual data, the decoding parameter, and macroblock (MB) processing information of an upper cluster by column, and splitting the information acquired by column into M number of functions to process the same.

Abstract translation: 公开了一种基于数据和功能分解方案的视频解码装置和方法。 基于数据和功能分割方案的视频解码装置包括：可变长度解码单元，对比特流执行可变长度解码和解析以获取残差数据和解码参数，并且逐行分割残留数据和解码参数; 并且N（N是2或更大的自然数）将数量分解解量化和逆离散余弦变换（IDCT），运动矢量预测，帧内预测和运动补偿，视频恢复和去块功能的簇数分为M个函数，获取 按照列逐列的残差数据，解码参数和宏块（MB）处理信息，并将通过列获取的信息拆分为M个函数以进行处理。

公开(公告)号：US07920429B2

公开(公告)日：2011-04-05

申请号：US12003548

申请日：2007-12-28

Applicant: Sung-Soo Chi ,  Jae-Jin Lee

Inventor： Sung-Soo Chi ,  Jae-Jin Lee

IPC: G11C16/06

CPC classification number: G11C11/4085 ,  G11C8/08

Abstract: A semiconductor memory device which includes: a voltage supplying unit for outputting a power source voltage as a driving source signal during a predetermined time, and then outputting a high voltage as the driving source signal in response to a driving control signal activated in response to an address signal; and a word line control unit for activating a word line at a voltage level of the driving source signal in response to the driving control signal.

Abstract translation: 一种半导体存储器件，包括：电压提供单元，用于在预定时间期间输出作为驱动源信号的电源电压，然后响应于响应于所述驱动源信号而被激活的驱动控制信号输出高电压作为驱动源信号 地址信号 以及字线控制单元，用于响应于驱动控制信号而在驱动源信号的电压电平下激活字线。

公开(公告)号：US20100252872A1

公开(公告)日：2010-10-07

申请号：US12820092

申请日：2010-06-21

Applicant: Hee Bok KANG ,  Jin Hong AHN ,  Jae Jin LEE

Inventor： Hee Bok KANG ,  Jin Hong AHN ,  Jae Jin LEE

IPC: H01L27/115

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

Abstract: A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers.

Abstract translation: 非易失性铁电存储器件包括多个单元阵列，其中多个单元阵列中的每一个包括：底部字线; 分别形成在底部字线上的多个绝缘层; 浮动沟道层，包括位于所述多个绝缘层上的多个沟道区和与所述多个沟道区交替电连接的多个漏极和源极区; 分别形成在所述浮动沟道层的所述多个沟道区上的多个铁电层; 以及分别形成在多个铁电体层上的多个字线。 根据多个铁电层的极性状态，单元阵列通过对多个沟道区域引起不同的沟道电阻来读取和写入多个数据。

公开(公告)号：US20100074542A1

公开(公告)日：2010-03-25

申请号：US12368814

申请日：2009-02-10

Applicant: Jae Jin LEE ,  Moo Kyoung CHUNG ,  Seung Hyun CHO ,  Kyung Su KIM ,  Jun Young LEE ,  Seong Mo PARK ,  Nak Woong EUM

Inventor： Jae Jin LEE ,  Moo Kyoung CHUNG ,  Seung Hyun CHO ,  Kyung Su KIM ,  Jun Young LEE ,  Seong Mo PARK ,  Nak Woong EUM

IPC: G06F7/06 ,  G06F17/30

CPC classification number: H04N19/426 ,  H04N19/44 ,  H04N19/91

Abstract: Provided are an apparatus for decoding a minimum memory access-based context adaptive variable length code (CAVLC) of the moving picture compression standard, H.264, and a table search method for decoding a context adaptive variable length code using the same. The apparatus for decoding a context adaptive variable length code may be useful to improve an overall decoding speed since the repeated memory accesses may be reduced to 2 cycles of memory accesses by reconstructing a context adaptive variable length code table of first decoding information (TrailingOnes) and second decoding information (TotalCoefficient) into 2-step tables and storing the reconstructed 2-step tables in advance and performing a table search to decode the first decoding information and the second decoding information, by using the information stored in the 2-step tables, depending on whether the remaining bits except for the number of leading zero are present in the inputted bit stream.

Abstract translation: 提供了一种用于解码运动图像压缩标准H.264的最小存储器访问上下文自适应可变长度码（CAVLC）的装置，以及用于使用其进行上下文自适应可变长度码的解码的表搜索方法。 用于对上下文自适应可变长度码进行解码的装置对于提高整体解码速度可能是有用的，因为通过重建第一解码信息（TrailingOnes）的上下文自适应可变长度码表，可以将重复的存储器访问减少到2个周期的存储器访问， 第二解码信息（TotalCoefficient）到2步表中，并且通过使用存储在2步表中的信息，预先存储重建的两步表并执行表搜索以解码第一解码信息和第二解码信息， 取决于在输入的比特流中是否存在除了前导零的数目之外的剩余比特。

公开(公告)号：US20090138684A1

公开(公告)日：2009-05-28

申请号：US12181769

申请日：2008-07-29

Applicant: Jae Jin Lee ,  Jun Young Lee ,  Moo Kyoung Chung ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Jae Jin Lee ,  Jun Young Lee ,  Moo Kyoung Chung ,  Seong Mo Park ,  Nak Woong Eum

IPC: G06F9/30

CPC classification number: H04N19/42 ,  H04N19/44 ,  H04N19/91

Abstract: Provided is an H.264 Context Adaptive Variable Length Coding (CAVLC) decoding method based on an Application-Specific Instruction-set Processor (ASIP). The H.264 CAVLC decoding method includes determining a plurality of comparison bit strings on the basis of a table of a decoding coefficient, storing lengths of the comparison bit strings in a first register, storing code values of the comparison bit strings in a second register, comparing an input bit stream with the comparison bit strings based on the lengths and code values of the comparison bit strings, and determining value of the decoding coefficient according to a result of comparison between the input bit stream and the comparison bit strings. The method extracts a decoding coefficient using a register in an ASIP without accessing a memory and prevents a reduction in speed caused by memory access, thereby increasing the decoding speed of an H.264 decoder.

Abstract translation: 提供了一种基于应用特定指令集处理器（ASIP）的H.264上下文自适应可变长度编码（CAVLC）解码方法。 H.264 CAVLC解码方法包括：基于解码系数的表确定多个比较比特串，将比较比特列的长度存储在第一寄存器中，将比较比特列的代码值存储在第二寄存器 根据比较比特串的长度和码值比较输入比特流与比较比特串，并根据输入比特流和比较比特串之间的比较结果确定解码系数的值。 该方法使用ASIP中的寄存器提取解码系数，而不访问存储器，并且防止由存储器访问引起的速度降低，从而提高H.264解码器的解码速度。

公开(公告)号：US07521978B2

公开(公告)日：2009-04-21

申请号：US11479290

申请日：2006-06-29

Applicant: Dong-Hwan Kim ,  Si-Nae Kim ,  Kae-Dal Kwack ,  Jae-Jin Lee

Inventor： Dong-Hwan Kim ,  Si-Nae Kim ,  Kae-Dal Kwack ,  Jae-Jin Lee

IPC: G06F1/04

CPC classification number: G06F1/10

Abstract: A clock driver is provided. A first driving unit is configured with a plurality of drivers and receives a first clock signal to drive a first pumping clock. A second driving unit is configured with a plurality of drivers and receives a second clock signal to drive a second pumping clock. A charge recycling switch is connected between an output terminal of the first driving unit and an output terminal of the second driving unit. A switch controller selectively transfers an input clock signal of the first or second driving unit to the charge recycling switch in response to the first and second pumping clock signals.

Abstract translation: 提供时钟驱动程序。 第一驱动单元配置有多个驱动器并且接收第一时钟信号以驱动第一泵送时钟。 第二驱动单元配置有多个驱动器并且接收第二时钟信号以驱动第二抽时钟。 电荷循环开关连接在第一驱动单元的输出端和第二驱动单元的输出端之间。 开关控制器响应于第一和第二抽吸时钟信号选择性地将第一或第二驱动单元的输入时钟信号传送到电荷再循环开关。

公开(公告)号：US07449944B2

公开(公告)日：2008-11-11

申请号：US11321873

申请日：2005-12-30

Applicant: Sang-Jin Byeon ,  Jae-Jin Lee

Inventor： Sang-Jin Byeon ,  Jae-Jin Lee

IPC: G05F1/563 ,  H02M3/18

CPC classification number: G11C5/145 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: An internal voltage generator includes a high efficient charge pump. The internal voltage generator includes an oscillation signal generator for receiving a reference voltage and a pumping voltage to thereby output an oscillation signal, a pump control logic for outputting a pumping control signal and a precharge signal in response to the oscillation signal, and a charge pump for precharging the pair of bootstrapping node by connecting the pair of bootstrapping node in response to the precharge signal to thereby generate the pumping voltage of a predetermined level after precharging the pair of bootstrapping node into a level of the power supply voltage and charge sharing the pair of bootstrapping node and the pumping voltage in response to the precharge signal. Herein, the pumping control signal controls a pumping operation and the precharge signal precharges a pair of bootstrapping node for generating the pumping voltage by pumping a power supply voltage.

Abstract translation: 内部电压发生器包括高效电荷泵。 内部电压发生器包括用于接收参考电压和泵浦电压从而输出振荡信号的振荡信号发生器，用于响应于振荡信号输出泵控制信号和预充电信号的泵控制逻辑，以及电荷泵 用于通过响应于预充电信号连接一对自举节点来预充电一对自举节点，从而在将一对自举节点预充电到电源电压的电平和电荷共享对之后产生预定电平的泵浦电压 的自举节点和响应于预充电信号的抽运电压。 这里，泵送控制信号控制泵送操作，并且预充电信号通过泵送电源电压来预充电一对自举节点以产生泵送电压。

公开(公告)号：US07379502B2

公开(公告)日：2008-05-27

申请号：US10039794

申请日：2001-10-19

Applicant: Heui Gi Son ,  Bo Hyung Lee ,  Jae Jin Lee ,  Joo Hyun Lee

Inventor： Heui Gi Son ,  Bo Hyung Lee ,  Jae Jin Lee ,  Joo Hyun Lee

IPC: H04B14/04

CPC classification number: H03M5/145 ,  G11B20/1426 ,  G11B2020/1461 ,  G11B2020/1465 ,  G11B2020/1469 ,  H03M7/46

Abstract: Disclosed is a method of digital data conversion. The method includes binding input digital data into unit blocks constituted by a plurality of bytes, modulation-coding each byte of the input data blocks by using a code conversion table, and allocating a merging bit in block unit for the modulation-coded input data in block unit.

Abstract translation: 公开了一种数字数据转换的方法。 该方法包括将输入数字数据结合成由多个字节构成的单位块，通过使用代码转换表对输入数据块的每个字节进行调制编码，并以块为单位分配用于调制编码的输入数据的合并位 块单位。