公开(公告)号：US10193379B2

公开(公告)日：2019-01-29

申请号：US14893374

申请日：2014-11-05

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee ,  Sung Wan Ro ,  Kyo Beum Lee

IPC: H02J9/06

Abstract: Disclosed is a direct current uninterruptible power supply system. The direct current uninterruptible power supply system according to an embodiment of the present invention is electrically connected to a direct current power converter for converting commercial alternating current power to direct current power, in order to: supply the direct current power to a load and charge an auxiliary power supply device therein with the direct current power. In the case of a short circuit of the direct current power converter due to a current leakage or breakage of the direct current power converter, or if the direct current power converter is disconnected, the direct current uninterruptible power supply system enables the auxiliary power supply device to constantly supply power to the load while completely blocking the electrical connection to the direct current power converter.

公开(公告)号：US09397391B2

公开(公告)日：2016-07-19

申请号：US13885374

申请日：2011-11-15

Applicant: Yang-Ki Hong ,  Seok Bae ,  Jae-Jin Lee

Inventor： Yang-Ki Hong ,  Seok Bae ,  Jae-Jin Lee

IPC: B05D5/12 ,  H01Q1/36 ,  H01F1/34 ,  H01Q1/22 ,  H01Q1/38

CPC classification number: H01Q1/364 ,  H01F1/348 ,  H01Q1/2283 ,  H01Q1/38 ,  Y10T29/49016

Abstract: An antenna is fabricated using an M-type hexaferrite, such as a tin (Sn) and zinc (Zn) substituted M-type strontium hexaferrite (Sn/Zn-substituted SrM: SrFe12−2xZnxSnxO19), thereby enabling antenna miniaturization, broad bandwidth, and high gain. In one embodiment, an antenna system has a substrate and a chip antenna formed on the substrate. The system also has a conductive radiator contacting the chip antenna, and the chip antenna comprises an M-type strontium hexaferrite for which Fe cations are substituted with tin (Sn) and zinc (Zn) to achieve soft magnetic properties for the antenna. Thus, the coercivity and permeability are lower and higher, respectively, than those of pure SrM. Such fabricated hexaferrite chip antennas have broadband characteristics and show good radiation performance at various frequencies, including in the GHz frequency range.

Abstract translation: 使用诸如锡（Sn）和锌（Zn）取代的M型六方铁氧锶（Sn / Zn取代的SrM：SrFe12-2xZnxSnxO19）的M型六铁素制造天线，从而使天线小型化，宽带宽， 和高增益。 在一个实施例中，天线系统具有形成在基板上的基板和芯片天线。 该系统还具有与芯片天线接触的导电散热器，并且芯片天线包括M型六方铁氧体，其中Fe阳离子被锡（Sn）和锌（Zn）所取代，以获得天线的软磁特性。 因此，矫顽力和渗透率分别低于纯SrM的矫顽力和渗透率。 这种制造的六方铁芯片天线具有宽带特性，并且在各种频率（包括在GHz频率范围内）表现出良好的辐射性能。

公开(公告)号：US20160006297A1

公开(公告)日：2016-01-07

申请号：US14435532

申请日：2013-10-08

Applicant: Jae Jin LEE

Inventor： Jae Jin LEE ,  Kyo Beum LEE

IPC: H02J9/06 ,  H02J7/00

CPC classification number: H02J9/061 ,  H02J7/0068

Abstract: Provided is an uninterruptible direct current (DC) power supply system, which includes a first connection unit electrically connected to a DC power conversion system which converts prevailing AC power into the DC power, a second connection unit which is electrically connected to the load and supplies the DC power to the load, an auxiliary power supply charged by the DC power, and an uninterruptible control unit which supplies the DC power supplied from the DC power conversion system normally connected to the first connection unit to the load through the second connection unit, charges the auxiliary power supply, and controls power to be continuously supplied to the load while perfectly cutting off electrical connection between the DC power conversion system and the auxiliary power supply when the DC power conversion system is disconnected from the first connection unit, is damaged, or short-circuits.

Abstract translation: 提供一种不间断直流（DC）电源系统，其包括电连接到直流电力转换系统的第一连接单元，该直流电力转换系统将主要的交流电力转换为直流电力;第二连接单元，电连接到负载和供应 负载的直流电力，由直流电源充电的辅助电源;以及不间断控制单元，其通过第二连接单元将正常连接到第一连接单元的直流电力转换系统提供的直流电力提供给负载， 对辅助电源进行充电，并且当DC电力转换系统与第一连接单元断开连接时，在完全切断直流电力转换系统与辅助电源之间的电气连接的同时，控制向负载连续供电的电力被损坏， 或短路。

公开(公告)号：US09190723B1

公开(公告)日：2015-11-17

申请号：US13247515

申请日：2011-09-28

Applicant: Yang-Ki Hong ,  Seok Bae ,  Jae-Jin Lee

Inventor： Yang-Ki Hong ,  Seok Bae ,  Jae-Jin Lee

IPC: H01Q1/52 ,  H01Q21/28

CPC classification number: H01Q9/42 ,  H01Q1/52 ,  H01Q1/521 ,  H01Q17/00 ,  H01Q21/28 ,  H04B7/0413

Abstract: A Multi-Input-Multi-Output (MIMO) system has multiple radiation elements and absorbers disposed on a substrate. The absorbers are positioned about the radiation elements to reduce the interference between the radiation elements. Use of the absorbers permits interference levels comparable to conventional MIMO systems using spatial diversity without requiring the antennas to be separated by at least one-half of the wavelength of the communicated signals. A ground plane on the substrate is also positioned on the substrate to enhance antenna system performance.

Abstract translation: 多输入多输出（MIMO）系统具有设置在基板上的多个辐射元件和吸收体。 吸收体围绕辐射元件定位以减小辐射元件之间的干扰。 吸收体的使用允许与使用空间分集的常规MIMO系统相当的干扰水平，而不需要将天线分离通信信号的波长的至少一半。 衬底上的接地平面也位于衬底上，以增强天线系统性能。

公开(公告)号：US08823041B2

公开(公告)日：2014-09-02

申请号：US13567776

申请日：2012-08-06

Applicant: Byoung Sung Kim ,  Sang Eun Lim ,  Jae Jin Lee ,  Yeoun Chul Son

Inventor： Byoung Sung Kim ,  Sang Eun Lim ,  Jae Jin Lee ,  Yeoun Chul Son

IPC: H01L33/00 ,  H01L33/62 ,  H01L33/48 ,  H01L33/64 ,  F21V29/00 ,  F21Y101/02

CPC classification number: H01L33/62 ,  F21V29/74 ,  F21V29/75 ,  F21Y2115/10 ,  H01L33/486 ,  H01L33/642 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49107 ,  H01L2924/00014

Abstract: Exemplary embodiments of the present invention provide a light emitting diode package including a light emitting diode chip, a lead frame having a chip area on which the light emitting diode chip is arranged, and a package body supporting the lead frame. The lead frame includes a first terminal group arranged at a first side of the chip area and a second terminal group arranged at a second side of the chip area. The first terminal group and the second terminal group each include a first terminal connected to the chip area and a second terminal separated from the chip area, and the width of the first terminal is different than the width of the second terminal outside the package body.

Abstract translation: 本发明的示例性实施例提供一种包括发光二极管芯片的发光二极管封装，其上布置有发光二极管芯片的芯片区域的引线框架和支撑引线框架的封装体。 引线框架包括布置在芯片区域的第一侧的第一端子组和布置在芯片区域的第二侧的第二端子组。 第一端子组和第二端子组各自包括连接到芯片区域的第一端子和与芯片区域分离的第二端子，并且第一端子的宽度不同于封装体外部的第二端子的宽度。

公开(公告)号：US20130234326A1

公开(公告)日：2013-09-12

申请号：US13604481

申请日：2012-09-05

Applicant: Chul KIM ,  Jae Jin LEE ,  Jong Chern LEE

Inventor： Chul KIM ,  Jae Jin LEE ,  Jong Chern LEE

IPC: H01L23/00 ,  H01L21/82

CPC classification number: H01L23/562 ,  H01L21/82 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor apparatus comprises of a first semiconductor chip having a through silicon via (TSV) and a second semiconductor chip also having a TSV, wherein the respective semiconductor chips are stacked vertically and are connected through a conductive connection member without the assistance of an additional bump between the conductive connection member and the second semiconductor chip.

Abstract translation: 半导体装置包括具有贯通硅通孔（TSV）的第一半导体芯片和也具有TSV的第二半导体芯片，其中各个半导体芯片垂直堆叠并通过导电连接构件连接，而无需附加凸块 在导电连接部件和第二半导体芯片之间。

公开(公告)号：US20130105851A1

公开(公告)日：2013-05-02

申请号：US13340867

申请日：2011-12-30

Applicant: Byoung Sung KIM ,  Sang Eun LIM ,  Jae Jin LEE ,  Yeoun Chul SON

Inventor： Byoung Sung KIM ,  Sang Eun LIM ,  Jae Jin LEE ,  Yeoun Chul SON

IPC: H01L33/62

CPC classification number: H01L33/486 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49107 ,  H05K1/0268 ,  H05K1/181 ,  H05K3/3426 ,  H05K2201/09427 ,  H05K2201/10106 ,  Y02P70/613 ,  H01L2924/00014

Abstract: Exemplary embodiments of the present invention provide a light emitting diode package including a light emitting diode chip, a lead frame having a chip area on which the light emitting diode chip is arranged, and a package body supporting the lead frame. The lead frame includes a first terminal group arranged at a first side of the chip area and a second terminal group arranged at a second side of the chip area. The first terminal group and the second terminal group each include a first terminal and a second terminal, and in at least one of the first terminal group and the second terminal group, the first terminal is connected to the chip area and the second terminal is separated from the chip area. The first terminal has a first width, the second terminal has a second width, and the first width is different than the second width.

Abstract translation: 本发明的示例性实施例提供一种包括发光二极管芯片的发光二极管封装，其上布置有发光二极管芯片的芯片区域的引线框架和支撑引线框架的封装体。 引线框架包括布置在芯片区域的第一侧的第一端子组和布置在芯片区域的第二侧的第二端子组。 第一端子组和第二端子组各自包括第一端子和第二端子，并且在第一端子组和第二端子组中的至少一个中，第一端子连接到芯片区域，并且第二端子被分离 从芯片区域。 第一端子具有第一宽度，第二端子具有第二宽度，并且第一宽度不同于第二宽度。

公开(公告)号：US08369122B2

公开(公告)日：2013-02-05

申请号：US12838332

申请日：2010-07-16

Applicant: Sang Jin Byeon ,  Jae Jin Lee

Inventor： Sang Jin Byeon ,  Jae Jin Lee

IPC: G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C8/00

CPC classification number: H03L7/00

Abstract: A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same.

Abstract translation: 半导体装置具有堆叠在其中的多个芯片。 用于控制多个芯片的读取操作的读取控制信号与参考时钟同步，使得从应用读取命令到多个芯片中的每一个的数据输出所花费的时间保持基本相同。

公开(公告)号：US20120182042A1

公开(公告)日：2012-07-19

申请号：US13162676

申请日：2011-06-17

Applicant: Chun Seok JEONG ,  Jae Jin LEE

Inventor： Chun Seok JEONG ,  Jae Jin LEE

IPC: H03K19/003

CPC classification number: G11C7/20 ,  G11C29/883 ,  G11C2029/4402 ,  H01L2224/16

Abstract: A semiconductor apparatus having first and second chips includes a first operation unit disposed in the first chip, and is configured to perform a predetermined arithmetic operation for an initial code according to a first repair signal and generate a first operation code; and a second operation unit disposed in the second chip, and configured to perform the predetermined arithmetic operation for the first operation code according to a second repair signal and generate a second operation code.

Abstract translation: 具有第一和第二芯片的半导体装置包括设置在第一芯片中的第一操作单元，并且被配置为根据第一修复信号对初始码执行预定的算术运算，并生成第一操作码; 以及第二操作单元，设置在所述第二芯片中，并且被配置为根据第二修复信号对所述第一操作码执行所述预定算术运算，并生成第二操作码。

公开(公告)号：US08022784B2

公开(公告)日：2011-09-20

申请号：US12433116

申请日：2009-04-30

Applicant: Jae Jin Lee ,  Chul Soon Park ,  Dong Yun Jung ,  Ki Chan Eun

Inventor： Jae Jin Lee ,  Chul Soon Park ,  Dong Yun Jung ,  Ki Chan Eun

IPC: H01P5/107

CPC classification number: H01P5/107

Abstract: A wireless communication module includes a plurality of monolithic millimeter-wave integrated circuits (MMICs) for signal processing attached to the top surface of a multi-layer low temperature co-fired ceramic substrate; a planar transmission line formed on the top surface of the multi-layer substrate for communications between the MMICs; a metal base attached to the bottom surface of the multi-layer substrate and having an opening to which an antenna is attached; a plurality of vias for connecting the metal base and the planar transmission line within the multi-layer substrate to establish a uniform potential on a ground plane of the multi-layer substrate; an embedded waveguide formed in the opening surrounded with the vias within the multi-layer substrate; and a planar transmission line-to-waveguide transition apparatus for the transition of waves between the planar transmission line and the embedded waveguide.

Abstract translation: 无线通信模块包括多个单层毫米波集成电路（MMIC），用于信号处理，附接到多层低温共烧陶瓷衬底的顶表面; 形成在所述多层基板的上表面上用于MMIC之间的通信的平面传输线; 金属基底，附着在多层基板的底面上，并具有安装有天线的开口; 用于连接多层基板内的金属基底和平面传输线的多个通孔，以在多层基底的接地平面上建立均匀的电位; 在所述开口中形成的嵌入式波导，所述开口被所述多层基板内的通孔包围; 以及用于在平面传输线和嵌入式波导之间转换波的平面传输线到波导转换装置。