公开(公告)号：US20090206385A1

公开(公告)日：2009-08-20

申请号：US12370792

申请日：2009-02-13

申请人： Tae-Whan KIM ,  Kae-Dal KWACK ,  Sang-Su PARK

发明人： Tae-Whan KIM ,  Kae-Dal KWACK ,  Sang-Su PARK

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

摘要翻译： 非易失性存储器件包括半导体衬底，第一和第二控制栅极以及第一和第二电荷存储模式。 半导体衬底包括具有源极区，漏极区和位于源极和漏极区之间的沟道区的突出的有源管脚。 第一控制栅极位于沟道区的第一侧壁上，第二控制栅位于沟道区的第二侧壁上。 第二控制栅极与第一控制栅极分离。 第一电荷存储图案位于第一侧壁和第一控制栅极之间，第二电荷存储图案位于第二侧壁和第二控制栅极之间。

公开(公告)号：US20050057567A1

公开(公告)日：2005-03-17

申请号：US10871140

申请日：2004-06-18

申请人： Jung-Young Son ,  Sang-Hoon Shin ,  Yong-Jin Choi ,  Saveliev Vladmir ,  Kae-Dal Kwack

发明人： Jung-Young Son ,  Sang-Hoon Shin ,  Yong-Jin Choi ,  Saveliev Vladmir ,  Kae-Dal Kwack

IPC分类号： G02B27/22 ,  G06T11/20

CPC分类号： G06T11/203 ,  H04N13/305 ,  H04N13/31 ,  H04N13/317

摘要： A method of forming pixel cell for three-dimensional image display is provided. The method of forming pixel cell according to this invention relates to a method of forming pixel-cell in a three-dimensional image display system including an image display panel in which a plurality of unit patterns are arranged in a vertical direction and horizontal direction and an optical plate having repetitive pattern. The method according to this invention comprising regarding each side of rhombus pattern having an arbitrary vertex angle as a straight line having a predetermined slant; calculating a number of unit pattern in vertical direction and a number of unit pattern in horizontal direction, corresponding to said predetermined slant; approximating said predetermined slant to stepped patterns with said number of unit pattern in vertical direction and said number of unit pattern in horizontal direction; and forming said pixel cell using said stepped patterns. And integer-numbered unit patterns are arranged in said pixel cell. By the present invention, quality degradation of a three-dimensional image due to Moire patterns is reduced.

摘要翻译： 提供一种形成用于三维图像显示的像素单元的方法。 根据本发明的形成像素单元的方法涉及一种在三维图像显示系统中形成像素单元的方法，该三维图像显示系统包括在垂直方向和水平方向上布置多个单元图案的图像显示面板，以及 具有重复图案的光学板。 根据本发明的方法包括将具有任意顶角的菱形图案的每一边作为具有预定倾斜度的直线; 计算垂直方向上的单位图案的数量和水平方向上的单位图案的数量，对应于所述预定倾斜度; 将所述预定倾斜近似为具有垂直方向上的所述单位图案数量和所述单位图案在水平方向上的数量的阶梯图案; 以及使用所述阶梯图案形成所述像素单元。 并且整数单位图案被布置在所述像素单元中。 通过本发明，由于莫尔图案导致的三维图像的质量下降降低。

公开(公告)号：US07521978B2

公开(公告)日：2009-04-21

申请号：US11479290

申请日：2006-06-29

申请人： Dong-Hwan Kim ,  Si-Nae Kim ,  Kae-Dal Kwack ,  Jae-Jin Lee

发明人： Dong-Hwan Kim ,  Si-Nae Kim ,  Kae-Dal Kwack ,  Jae-Jin Lee

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A clock driver is provided. A first driving unit is configured with a plurality of drivers and receives a first clock signal to drive a first pumping clock. A second driving unit is configured with a plurality of drivers and receives a second clock signal to drive a second pumping clock. A charge recycling switch is connected between an output terminal of the first driving unit and an output terminal of the second driving unit. A switch controller selectively transfers an input clock signal of the first or second driving unit to the charge recycling switch in response to the first and second pumping clock signals.

摘要翻译： 提供时钟驱动程序。 第一驱动单元配置有多个驱动器并且接收第一时钟信号以驱动第一泵送时钟。 第二驱动单元配置有多个驱动器并且接收第二时钟信号以驱动第二抽时钟。 电荷循环开关连接在第一驱动单元的输出端和第二驱动单元的输出端之间。 开关控制器响应于第一和第二抽吸时钟信号选择性地将第一或第二驱动单元的输入时钟信号传送到电荷再循环开关。

公开(公告)号：US07927951B2

公开(公告)日：2011-04-19

申请号：US12955984

申请日：2010-11-30

申请人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Sang-Su Park

发明人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Sang-Su Park

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

摘要翻译： 非易失性存储器件包括半导体衬底，第一和第二控制栅极以及第一和第二电荷存储模式。 半导体衬底包括具有源极区，漏极区和位于源极和漏极区之间的沟道区的突出的有源管脚。 第一控制栅极位于沟道区的第一侧壁上，第二控制栅位于沟道区的第二侧壁上。 第二控制栅极与第一控制栅极分离。 第一电荷存储图案位于第一侧壁和第一控制栅极之间，第二电荷存储图案位于第二侧壁和第二控制栅极之间。

公开(公告)号：US07880661B2

公开(公告)日：2011-02-01

申请号：US11819816

申请日：2007-06-29

申请人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Joong-Sik Kih ,  Jong-Man Im ,  Jae-Woong Choi ,  Myoung-Jun Chai ,  Kae-Dal Kwack

发明人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Joong-Sik Kih ,  Jong-Man Im ,  Jae-Woong Choi ,  Myoung-Jun Chai ,  Kae-Dal Kwack

IPC分类号： H03M1/50

CPC分类号： H03M1/56 ,  G01K7/01 ,  G01K2219/00

摘要： An on-die thermal sensor includes an integrating analog-digital converter not requiring a negative reference voltage input. The on die thermal sensor includes a band gap unit, an integrating unit and a counting unit. The band gap unit senses a temperature to output a first voltage corresponding to the sensed temperature. The integrating unit integrates a difference between a reference voltage and a comparing voltage to output a second voltage wherein the comparing voltage has a voltage level higher than that of the reference voltage. The counting unit counts clocks of a clock signal input thereto until the second voltage reaches the first voltage, thereby outputting a thermal code corresponding to the voltage level of the first voltage.

摘要翻译： 片上热传感器包括不需要负参考电压输入的积分模数转换器。 管芯热传感器包括带隙单元，积分单元和计数单元。 带隙单元感测温度以输出对应于感测温度的第一电压。 积分单元将参考电压和比较电压之间的差分相加以输出第二电压，其中比较电压的电压电平高于参考电压的电压电平。 计数单元对输入的时钟信号的时钟进行计数，直到第二电压达到第一电压，从而输出与第一电压的电压电平对应的热代码。

公开(公告)号：US07034847B2

公开(公告)日：2006-04-25

申请号：US10871140

申请日：2004-06-18

申请人： Jung-Young Son ,  Sang-Hoon Shin ,  Yong-Jin Choi ,  Saveliev Vladmir ,  Kae-Dal Kwack

发明人： Jung-Young Son ,  Sang-Hoon Shin ,  Yong-Jin Choi ,  Saveliev Vladmir ,  Kae-Dal Kwack

IPC分类号： G09G5/00

CPC分类号： G06T11/203 ,  H04N13/305 ,  H04N13/31 ,  H04N13/317

摘要： A method of forming pixel cell for three-dimensional image display is provided. The method of forming pixel cell according to this invention relates to a method of forming pixel-cell in a three-dimensional image display system including an image display panel in which a plurality of unit patterns are arranged in a vertical direction and horizontal direction and an optical plate having repetitive pattern. The method according to this invention comprising regarding each side of rhombus pattern having an arbitrary vertex angle as a straight line having a predetermined slant; calculating a number of unit pattern in vertical direction and a number of unit pattern in horizontal direction, corresponding to said predetermined slant; approximating said predetermined slant to stepped patterns with said number of unit pattern in vertical direction and said number of unit pattern in horizontal direction; and forming said pixel cell using said stepped patterns. And integer-numbered unit patterns are arranged in said pixel cell. By the present invention, quality degradation of a three-dimensional image due to Moire patterns is reduced.

摘要翻译： 提供一种形成用于三维图像显示的像素单元的方法。 根据本发明的形成像素单元的方法涉及一种在三维图像显示系统中形成像素单元的方法，该三维图像显示系统包括在垂直方向和水平方向上布置多个单元图案的图像显示面板，以及 具有重复图案的光学板。 根据本发明的方法包括将具有任意顶角的菱形图案的每一边作为具有预定倾斜度的直线; 计算垂直方向上的单位图案的数量和水平方向上的单位图案的数量，对应于所述预定倾斜度; 将所述预定倾斜近似为具有垂直方向上的所述单位图案数量和所述单位图案在水平方向上的数量的阶梯图案; 以及使用所述阶梯图案形成所述像素单元。 并且整数单位图案被布置在所述像素单元中。 通过本发明，由于莫尔图案导致的三维图像的质量下降降低。

公开(公告)号：US06914388B2

公开(公告)日：2005-07-05

申请号：US10668206

申请日：2003-09-24

申请人： Hong-Jae Shin ,  Kae-Dal Kwack

发明人： Hong-Jae Shin ,  Kae-Dal Kwack

IPC分类号： H01L51/50 ,  G09G3/10 ,  G09G3/20 ,  G09G3/30 ,  G09G3/32 ,  H05B33/14

CPC分类号： G09G3/3216 ,  G09G3/3266 ,  G09G2320/0252 ,  G09G2330/021

摘要： There are provided an organic light emitting diode (OLED) display driving apparatus and a driving method thereof, in which the OLED display panel driving apparatus of a passive matrix type is configured such that its scan driving circuit has 3-state output, and the cathode lines, selected when the scan driving circuit performs a scan operation, maintain grounding, and after data-applied OLED emits light, are switched in a high voltage, and execute a refresh operation to initialize the pixel charges, and with the high impedance state maintained, non-selective common cathode lines turn into a high impedance state so as to remove the parasitic capacitance elements, and reduce the capacitance element functioning as the load of the data driving circuit connected to the OLED anode lines, and without the use of precharge method of maintaining the anode lines above a predetermined voltage quickly by using a voltage source, and applying data by using a current source, the anode lines can be charged within a short time just by necessary current for the lightening of the OLED so as to reduce the power consumption of the data driving circuit, and increase the operation speed.

摘要翻译： 提供了一种有机发光二极管（OLED）显示驱动装置及其驱动方法，其中无源矩阵型的OLED显示面板驱动装置被配置为使得其扫描驱动电路具有3态输出，并且阴极 当扫描驱动电路执行扫描操作，保持接地并且在数据应用的OLED发光之后被选择的线路被切换为高电压，并且执行刷新操作以初始化像素电荷，并且保持高阻抗状态 ，非选择性公共阴极线变成高阻抗状态，以去除寄生电容元件，并且减小用作连接到OLED阳极线的数据驱动电路的负载的电容元件，并且不使用预充电方法 通过使用电压源将阳极线保持在预定电压以上，并且通过使用电流源施加数据，阳极线可以是cha 在短时间内仅仅通过用于减轻OLED的必要电流来减少数据驱动电路的功耗，并且提高了操作速度。

公开(公告)号：US08816944B2

公开(公告)日：2014-08-26

申请号：US11453529

申请日：2006-06-15

申请人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

发明人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

IPC分类号： G09G3/30

CPC分类号： G09G3/3283 ,  G09G3/2014 ,  G09G3/3216 ,  G09G2320/0233

摘要： A display device, which includes a plurality of pixels; a data driver for outputting data signals to the pixels; a bias current outputting unit for outputting a bias current having a predetermined magnitude; a plurality of driving current outputting units for outputting driving currents to the pixels; and a first switch connected between the bias current outputting unit and the driving current outputting units for selecting one of the driving current outputting units to connect to the bias current outputting unit, wherein the magnitudes of the driving currents are substantially the same as a magnitude of the bias current.

摘要翻译： 一种显示装置，包括多个像素; 用于将数据信号输出到像素的数据驱动器; 偏置电流输出单元，用于输出具有预定大小的偏置电流; 多个驱动电流输出单元，用于向像素输出驱动电流; 以及第一开关，连接在所述偏置电流输出单元和所述驱动电流输出单元之间，用于选择所述驱动电流输出单元中的一个连接到所述偏置电流输出单元，其中所述驱动电流的大小基本上与 偏置电流。

公开(公告)号：US20110216595A1

公开(公告)日：2011-09-08

申请号：US13063274

申请日：2009-09-09

申请人： Han-Sub Yoon ,  Jong-Suk Lee ,  Kae-Dal Kwack

发明人： Han-Sub Yoon ,  Jong-Suk Lee ,  Kae-Dal Kwack

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/16

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： A flash memory using hot carrier injection and a method of operating the same are provided. A plurality of strings constituting a page are formed on a single p-well and share the p-well. During a program operation, a string selection transistor is turned off, and electrons are accumulated in a source or drain region in response to a bias voltage applied to the p-well. Thereafter, the accumulated electrons are trapped in a charge trap layer of a memory cell in response to a program voltage applied through a word line. Also, during an erase operation, holes accumulated in response to a bias voltage applied to the p-well are trapped in the charge trap layer in response to an erase voltage. The flash memory performs NAND-type program and erase operations using hot carrier injection.

摘要翻译： 提供了使用热载流子注入的闪速存储器及其操作方法。 构成页面的多个串形成在单个p阱上并共享p阱。 在编程操作期间，串选择晶体管截止，并且响应于施加到p阱的偏置电压，电子在源或漏区中累积。 此后，响应于通过字线施加的编程电压，累积的电子被捕获在存储器单元的电荷陷阱层中。 此外，在擦除操作期间，响应于施加到p阱的偏置电压累积的空穴响应于擦除电压被捕获在电荷陷阱层中。 闪速存储器使用热载波注入来执行NAND型编程和擦除操作。

公开(公告)号：US20110075503A1

公开(公告)日：2011-03-31

申请号：US12650790

申请日：2009-12-31

申请人： Seung Wook KWACK ,  Kae Dal KWACK

发明人： Seung Wook KWACK ,  Kae Dal KWACK

IPC分类号： G11C8/00 ,  G11C8/10

CPC分类号： G11C7/12 ,  G11C8/10

摘要： A main decoding circuit includes a shared column selection signal generating unit and a switching unit. The shared column selection signal generating unit receives a column decoding signal to generate a shared column selection signal. The switching unit selectively provides the shared column selection signal to one of a column selection line of a first memory bank and a column selection line of a second memory bank in response to a bank selection signal.

摘要翻译： 主解码电路包括共享列选择信号生成单元和切换单元。 共享列选择信号生成单元接收列解码信号，生成共享列选择信号。 开关单元响应于存储体选择信号，选择性地将共享列选择信号提供给第一存储体的列选择行和第二存储体的列选择行之一。